TDC/TEL62 update M. Sozzi NA62 TDAQ WG meeting Bruxelles – 9/9/2010

What’s in a name TELL1 = Trigger Electronics for L1 (actually not used for L1 in LHCb) and William Tell The new board is a NA62 development → new name It is an upgrade/reworking not an entirely new board → similar name It is used for L0 trigger in NA62 → no “L1” in name Already referred to as “TELL” since two years → too different name would generate confusion Let’s call it: TEL62

TEL62 project Some delay in upgrade design Schematics now almost completed in Pisa New PCB layout to start at CERN mid september (~1 month time) Electrically compatible with original TELL1 (also daughter-cards) Upgraded FPGAs (Stratix I → Stratix III) Upgraded memories (DDR → DDR2) Additional static RAM General-purpose expansion connector Added second communication bus between PP and SL for trigger Some changes in power requirements: Timescale: have prototypes ready by end of this year Components procurement for 85 boards ongoing Still uncertain needs for: CHOD, MUV, (STRAWS), SAC/IRC

TEL62 project – two issues Power scheme completely changed more power on 48V desirable can halve power on +3.3V if needed (used for mezzanine cards: check…) Only issue is really for LKr/L0 (full crate) Difficult to estimate before prototype New FPGAs are more powerful but have lower fraction of I/O pins Keeping compatibility with LHCb mezzanine cards (2 different voltages) puts several constrains on PP-FPGAs We might be forced to use the next larger chips (more powerful but more expensive!)

TEL62: firmware Still using the test version of the firmware (no timestamped data buffering, no trigger primitive generation, no inter-board communication) Recent progress: Now using optical TTC clock Received TTC triggers Solved problems with latest LHCb framework New firmware: major effort, collaboration needed Not started yet Base (common) functionalities to be defined

TEL62: schedule Skeleton firmwarePisaNow to end of year Prototype(s)PisaEnd of year Intensive testingPisa + Roma TV + ?First half 2011 Pre-production?Roma TVSummer 2011? Components procurement Pisa + Roma TVFall Final base firmwarePisa + ?? Mass test setupRoma TV + ?? Full productionRoma TV? Firmware modsSub-detectors?

TDC board status Completed testing of the (single prototype) TDC board V3: cheaper FPGA 4 connectors only (1 per TDC) with SCSI3 connectors Major firmware change using TDC “trigger-matching mode” Correct (and adjustable) TDC core power voltage Overall cost (for few boards): 800EUR/board “HPTDC bug”: not seen in V3 (not even tweaking TDC core voltage), while reproducible in V2 boards “Bit errors” a high rates: not seen in V3, while reproducible in V2 boards Mounting errors: assembly by other firms up to 4x more expensive Final TDCB firmware under debugging

The cable saga: recap Episode 1: the connectors used for V1-V2 (and in the present test setup) are too fragile and unpractical Episode 2: Sturdy VHDCI connector (same as ALICE TOF “blue cable”) allow reducing the connectors by 2 (cannot use same ALICE TOF “blue cable” by Amphenol). Episode 3: Amphenol offers an affordable solution with same kind of cable/connector, TDC board V3 connections are chosen accordingly. Episode 4: Amphenol solution simply “evaporates” Episode 5: Technical Cable Concepts (CA) manifactures halogen-free SCSI cables with VHDCI Universal TM, 34-Pair, 68-Conductor, double-shielded cable

An end (?) to the cable saga Choose standard SCSI pinout on VHDCI (different from Amphenol solution, requires new TDCB but simpler/cheaper) “Official” after TDCB V4 available and final cables tested for performance 5m x 400 cables halogen- free standard SCSI: 80 USD/cable 8 weeks for 400 cables 2 halogen-free 6m-length prototypes in Pisa, impedance tested OK

TDC boards prospects The (hopefully final) version 4 is being produced Almost identical to V3: Different (standard SCSI) pinout, same connectors Minor fixes for HPTDC JTAG error 20 PCBs expected next week Will make another try with the same mounting company (with extra care and automated mounting) Mount 2 boards now and (up to 15) later. Who wants one? Final TDCB firmware under debugging (engineer leaving Nov 2010) Timescale: expect prototypes ready in ~1 month Production, numbers, spares ?

TDC: schedule Final prototypesPisaFall 2011 Complete firmwarePisaEnd of year Intensive testingPisa + Perugia + ?First half 2011 Components procurement PisaFall Mass test setupPisa ? (help needed)? Production(s)?Pisa?

TDC/TELL1 in test beams TDC/TELL1 prototype system used in two 2010 test beams: Intensively in STRAW chambers prototype test: 21/6 - 4/7/2010 Marginally in LAV test beam: 12/8 – 1/9 Hardware provided: Hybrid Hytec Crate, 1 TELL1, TDC board(s) V2, (old) cables, test version of the firmware, control and readout software Spreading the knowledge on the system See RICH/LAV WG talks for more info