1. Status of NA62 straw electronics and services Peter LICHARD, Johan Morant, Vito PALLADINO

2. Services All 4 chambers wired with HV, LV and data cables – Still need to close electrically all cable trays HV distribution – Worked from the start without a problem – Last week I cover tripping Wire, web, HV connector/cable? Data cables – Rather long but seems to be still OK for safe operation of cover link VME crates – No problems VME SBC – Had to be reinstalled with OS – Should we use boot server instead of local installation? – Painful ‘/afs’; local account? Patch panels – HV OK – LV - No lost ELMBs

3. Services MPOD – 4 MPODs installed and working – 1 HV module bad since delivery 3 channels + mess in crate Sent for reparation Using 2 8ch modules borrowed from Wiener instead – Safety features Safety loop works but ‘clear event’ not available on front panel Current trip works but must better understand how to set current_limit + time – Saw few trips recently Current DCS software is always disabling current limit For the rest of the run we must use factory software DSS – Using MPODs safety loop and current trip – Installed and tested

4. Covers 4 chambers work! – 1 cover has to be replaced Repeated from previous presentation Need to rebuild our ‘test rack’ and ‘test bench’ – VME crate from test rack is for chamber 4 – Need to keep test bench alive for (re-) tesing covers – Take 6U VME crate from the POOL – Johan will provide injection control and circuitry – In 154 we will keep Complete readout with straw prototype for development Cover test bench Spare covers, spare SRBs, patch panels (?) Components and cables

5. SRB Plans and reality – 1 st batch of 24 boards received end of July Good yield – 4 do not work at all, 2 some problems – 2 nd batch of 23 boards (1 not mounted) 26.11.2014 Bad yield – only ~10 working – 3 SRBs still missing to have a full detector equipped Trying to fix at least 3 boards till Wednesday

6. VME manager Front-End (To covers) Event Manager x2 Gb eth TTCrx Trigger Manager LOOKUP TABLE DDR3 ETH HISTOGRAM SRAM QDR CLOCK DELAY ALL COMPONENTS TESTED AND WORKING

7. SRB firmware Basic version with 0 bias (everything transmitted to pc- farm) seems to be now working and stable, even with high intensity beam Delayed due to number of problems mainly with FPGA compiler and IP cores – Bugs, poor or non-existent documentation – Lost cca 6 weeks Trigger matching FW – Time re-ordering code written Not tested – Still need to write DDR3 management and data packing – Debugging and testing phase – How relevant it is for this year?

8. Summary and plans Since July we are constantly developing and improving the straw readout system – Hardware (mainly testing and making alive new boards), DSS – Firmware (both cover and SRB) – Software (HUGE progress, DAQ, monitoring, run control, DCS, DSS, etc) Despite number of unexpected problems we have now a running stable system capable of taking data continuously even with high rate (20% nominal) in the last 2014 run week – Define procedure for T0 adjustment – Install and test data trigger matching – Define online and offline monitoring What MUST be done on SRB What can or can’t be done on SRB What must be done on PC How often and how much raw data we should store through VME interface for monitoring – Data analysis Feedback on detector performance Scan thresholds ? Scan HV ?