1. NA62 TDAQ WG Meeting News and usual stuff M. Sozzi CERN – 29/5/2009

2. Technical Design Let’s exploit the writing of the TD as the occasion to: consolidate specifications and requirements for TDAQ identify (assign) responsabilities

3. Overall scheme (Marco S.) Trigger simulation (Giuseppe R., Marco S.,...) L0 trigger simulation L1/L2 trigger simulation Requirements (Marco S.) Front-end electronics L0 trigger sub-detectors Higher-level triggers sub-detectors Pisa, … NOT COVERED Common infrastructure (Marco S., Valeri F.,...) Clock distribution L0 trigger distribution SPS interface / spill structure Data flow control Crates PC data input Local networking Common TELL1-based system NOT COVERED Pisa, … means: help needed Pisa, … 1/4

4. L0 central processor (Marco S.,...) CEDAR system (Cristina L.) Readout L1 processing LAV system (Riccardo F.) Readout L0 trigger L1 processing and trigger RICH system (Marco S., Perugia (who?)) Readout L0 trigger L1 processing and trigger CHANTI system (Fabio A.) ANTI Halo (Riccardo F.) CHOD (Massimo L.) SAV (Leandar L.) Pisa, … 2/4

5. Straw system (Hans D., Protvino (who?)...) Readout L1 processing and trigger MUV system (Rainer W., Moscow (who?)...) Readout L0 trigger L1 processing and trigger 3/4 LKr system (Bjorn H., Andrea S.) Clock distribution Readout L0 trigger L1 processing and trigger Gigatracker system (Angelo C.R.)

6. Online farm (Paolo V.) L2 trigger (Rainer W.,...) Event building L2 algorithms L1/L2 trigger distribution Data logging (Paolo V.) Data monitoring (...) 4/4

7. Items/responsibilities: tentative list - Detector front-end electronics: detector groups - TDC/TELL1 R/O & trigger development: INFN (PI, PG) - R/O & trig (TDC/TELL1) for RICH (cost): INFN (PI, PG) - R/O & trig? (TDC/TELL1) for LAV (cost + tailoring): INFN (PI, RM1, LNF) - R/O & trig (TDC/TELL1) for MUV/HAC (cost + tailoring): IHEP, INR, Mainz - R/O (TDC/TELL1 ?) for CEDAR (cost + tailoring): UK - R/O (TDC/TELL1) for STRAWs (cost + tailoring): CERN/JINR - R/O (TDC/TELL1) system for HODO, IRC, SAC: Bulgaria, others ? - R/O for GTK: INFN (TO, FE) - R/O for LKr: CERN - L0 trigger for LKr: INFN (RM2) - L0 supervisor: INFN (PI/RM2) - Central clock infrastructure: CERN ?, others ? - NA48 clock for LKr: CERN - Detector L1 PCs and L1 software: detector groups - Farm switch: Mainz - L2 farm: Mainz, others ? - L2 and event building software: Mainz ?, others ?

8. TELL1/TDC project: status and issues Final cable/connector choice: test beam Crates: 1 new offer for custom crate 4KE Flow control (XOFF): TD Re-engineering of NINO boards (for RICH; are STRAW interested???): proposed meeting end June (Firenze?)

9. 8 total available for NA62 (all should be there end of this week) 2 “old” partially working (at RICH test beam) 1 new with larger PP-FPGAs for testing 3 new standard ones (available) 2 new standard ones (not yet delivered) Requests: Pisa (2+1): Perugia (1): Roma3 (1): Roma1 (1): Louvain (1): Ferrara (1): Birmingham (1): TOTAL = 9 TELL1s (now) Available: 1 (to buy), 2 (to loan) Ask when you are ready to use it (power and server/software available)

10. We need to take care of building TELL1s: 1 offer available 2 nd firm evaluating Tentative plan: O(10) for testing/learning around end 2009 O(100) after final assessment by the collaboration Need to start procurement of components now! Need commitment of interested groups NOW Same for TDC boards: Final design: end of 2009 Building O(20)? Ask NOW TELL1s (future)

11. Urgent issues Responsability for TTC/clock Responsability for farm infrastructure Identify responsible person for each system using TDC/TELL1: organize a meeting soon start sharing firmware coding (Fast) MC simulation of L0 and L1/L2 required: each sub-detector should provide information on the L1 rejection factor/algorithms