1. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC http://hepnts1.rl.ac.uk/CMS_fed/Default.htm Presented by S. Quinton A PMC Based ADC Card for CMS Tracker Readout S.A. Baird, P. Burch, J.A. Coughlan, R. Halsall J. Hartley, W.J. Haynes, T. Parthipan CLRC Rutherford Appleton Laboratory Chilton, Didcot, Oxon OX11 0QX United Kingdom

2. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Microstrip Tracker Readout CMS Detector Microstrip Tracker : Silicon & MSGCs Total => 12,000,000 readout channels 70% CMS final data volume Analogue Optical Readout Front End Drivers FED in Counting Room Front End Pipelines APV on Detector Each ADC Channel on FED reads out 256 Microstrips Level 1 Trigger @ 100 kHz

3. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Front End Driver FED FED Basic Components: Optical Receivers ADCs Digital Signal Processing Error Detection Logic Central DAQ Interface Solution... Evaluation of Final FED Components Tracker Detector Prototyping in Labs & at Test Beams Requirements Now: Final FED Implementation in 2002: 9U VME 96 ADC channels per board

4. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC FED-PMC PCI Mezzanine Card PMC format Compact, Modular Commercial Bus PCI Plug on "off the shelf" VME Carriers Plug in PC/ Workstation Providing a Flexible & Cost Effective Solution for Test Beam and Lab setups Standards: Hardware : PMC/PCI Firmware : VHDL Software : C Libraries/Drivers

5. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC PMC Functionality 8 Electrical Input Channels (Differential/Single-ended) ADCs commercial using 9 bit @ 2 to 40 MHz Clock & Trigger LVDS via Front Panel (or Rear Connector) Data Buffer in DPM => 64K samples/channel Readout (during capture) via PCI Interface 32 bit @ 33 MHz FPGA with VHDL for Flexible Architecture (Plus... Test Functions, Clock Phase Adjustment, FPGA Flash Memory... ) => Readout PCI Detector Inputs =>

6. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Firmware FPGA Firmware stored in Flash Memory Core VHDL Blocks Local Bus DPM Interface Buffer Management FIFO & Counters control Register Interface Test Functions Future Extensions (for CMS) APV Auto-Synchronisation Higher Level DAQ Interface DMA Hit Finding Software tools are provided to enable... Firmware to be updated in situ via Network + User Defined Extensions... VHDL libraries available

7. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Functionality 8 x 9 Bit @ 40MHZ ADC Channels LVDS Clock & Trigger via Front Panel (TTC signals via J4) FPGA Synthesizable VHDL Library Comprehensive “C” Library for PMC Configuration & Readout Operating in “Scope mode” i.e. raw data for test beam PLX 9080 XC 4036 1 MB

8. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Test Beam 1999 Requirements Sampling @ 20MHz Scope Function Multiple Triggers within Frame APV Header recognition AIM => Production run ≈ 20 PMCs for CMS PMC in Lab Performance Benchmarks Implement known hardware modifications ( 3.3 V supply) APV sample reordering Hardware Trigger Throttle (Software) DMA readout Synchronisation errors (Software) FED Software integration in DAQ. Data formats...etc Multiple PMCs on carrier Signal timing adjustment procedures (calibrations) Now have 4 (+ 4) PMCs

9. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Summary Status Production run ≈ 20 PMCs for CMS We have 6 original PMCs. 2 of these now at CERN. Modifications needed for Test Beam ‘99 are under simulation. Implementation starting. Multiple FEDs. Porting Developer tools to Lynx. New version of User Library in development. New version of User Manual in progress.

10. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Timescales Documentation & Software http://hepnts1.rl.ac.uk/CMS_fed/Default.htm Implementing New Test Beam Requirements at RAL Integration at CERN in Tracker Test Bench with existing cards Hardware modifications implemented January PCB Manufacture 1st half February Assembly 2nd half February Boards tested in March 6? New Boards to CERN beginning April Production run of 20 PMCs 4 s s s

11. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC APV Frame and Triggers APV frame arrives at ? clocks after TTC trigger. Variable sample size. Problem with TTC Triggers arriving within APV frames. No APV Mux => FED sampling @ 40 MHz vs APV data @ 20 MHz. APV Header Synch in Xilinx.

12. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC APV Header Synch Verify TTC Triggers. APV Header Synch on one channel Option to sample @ 20 MHz. Modifications in Xilinx design.

13. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Other Issues? Requirements for Integration tests. Number of FEDs. Dates. Specification of inputs from TRI cards. Single ended 1.5 V pp. Special requirements for MSGCs vs Silicon. Connectors and cables. Trigger modes. APV Header synch. FED sampling @40 vs 20 MHz. Channel to channel synchronisation. APV errors. Raw data readout. Reduction. Finalise data formats. Procedure for timing adjustments. Calibration runs. Longer term... –Objectives of Beam Test. Single detectors vs Beam Telescope. Duration. –APV Mux +....

14. Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC CMS Tracker FED PMC Data Format Raw Data