1. Overview, remarks, lamentations, hope and despair M. Sozzi TDAQ WG meeting CERN - 4 June 2013 Introduction, news and appetizer

2. TDCB orders Final production now V5, V6 and V7 boards are all equivalent and usable Some detectors (e.g. CEDAR) need more boards than the number of channels due to high-rate channels Some detectors have 0 spares No common NA62 spares Cables ? Now or each group by himself Updated TWiki page

3. TEL62s - Availability All the boards sent to Pisa for repair will be repaired soon No other free boards (share?) until (pre-)production (when?)

4. TEL62s – HW Some rare JTAG chain problems GbE reset issue solved Change in DC/DC converters JTAG testing system to be better understood Looking for better mounting firm Firmware loading from software still broken (PG) FPGA resources enough? Cannot estimate without having at least prototype sub-detector firmware (only for LAV we have it)

5. TEL62s: upgrade? Moving from “standard” (110 LE) to “larger” (200 LE) FPGAs? Fully pin-compatible. 252 standard FPGAs (50%) bought Might be partially sold back for scrapping First naïve estimate: +850 EUR/board (+25%) Situation is still rather “fluid” A decision is needed soon, but we miss the information from sub-detectors

6. Firmware now Released “Version 1”: debugged/improved version of FW used in technical run, with same rate/window limitations, with “Pinzino effect” correction in TDCBs, full trigger primitive path (PP and SL), higher clock frequency, improved DDR controller, more diagnostics Available on web: FW files, source files, manual, TDSPY software code Soon to come: scripts, data acquisition program etc. → R. Piandani talk

7. Firmware soon Working on “Version 2”: improvements for higher rate, more windows, EOB readout of hit counters, etc. Expected for July → F. Spinella talk

8. Firmware future More? Inter-board communication: yes Hits reordering in TDCB ? Calibration/monitoring code for each SD? Trigger code for: RICH, CHOD, LAV, MUV3 ? Subdetector-specific code cannot be written in Pisa

9. TEL62s – FW to do (1) Data monitoring part (counters implemented, not tested) Writing of monitoring information into End-of-Burst events Reduce number of clock domains (speed up most of the blocks to 160 MHz) Test choke/error generation (and handling) Improve diagnostics Speed-up DDR writer and DDR reader (pipeline)

10. TEL62s – FW to do (2) Trigger primitive generation path: not foreseen for TR, finished and tested 2 days before the run ended, only partially tested with beam Test of TEL62-GPU communication and hardware-level synchronization Trigger primitive generation code for: CHOD (?), RICH (?), MUV (?) Inter-board communication for trigger primitive generation

11. Testing system TELL1 daughter card to pulse 4 TDCs developed at CERN (Riccardo/Gianluca) → G. Lamanna talk JTAG testing system for TEL62 assembled at Roma Tor Vergata Still needs qualification

12. Simulation We still have NO simulation of L1/L2 due to: lack of suitable MonteCarlo lack of manpower Serious implications on: Computing, L0TP Some work by B. Angelucci, with private pile-up code from G. Ruggiero

13. Data checks Independent checks are very useful to: spot errors identify further needs or clumsy parts improve documentation (online “Data formats” note)

14. Crates My understanding: Failures: forget about ? Noise: crates are up to specs, noise is too high for LAV, discussions on improvements

15. L0TP Hardware: interface board being built in Torino input firmware in Torino output firmware for base solution in Ferrara control firmware in Torino primitive simulation files provided by Pisa software prototype in Ferrara → A. Gianoli talk

16. Dry runs (1) 1-14 July 2013: CEDAR (Birmingham+), LAV (Frascati+), LKr (CERN), LKr/L0 (Roma Tor Vergata) TDAQ support from Pisa Need working infrastructure 1 week before (power, clock, network, DCS, slow control) (2) Autumn: October 2013 ? LKr (CERN), LKr/L0 (Roma Tor Vergata, Perugia), …? Send your requests/proposals NOW