1. Uli Schäfer 1 Production and QA issues Design Modules have been designed, with schematic capture and layout, in Mainz (B.Bauss) Cadence design tools, data format ODB++ (New!, lower risk?) Manufacture One-stop shop: component procurement, PCB manufacture, Module assembly Modules not passing acceptance test are returned for re-work Any re-work is done at the manufacturers expense Limit of one re-work per device Modules carry serial number, allowing for history being recorded Several JEM iterations have been successfully produced, though in the past agreements on re-work and proper acceptance tests have not been in place.

2. Uli Schäfer 2 Module production / cost Full order to go out immediately after passing review Pre-production of 4 modules (40 working days) Pre-production of all required daughter modules Upon successful tests, push button for full production Should take less than 30 working days  At CERN : 2nd of May Any bug fixes required after pre-production would incur delay of one month minimum JEMs required in ATLAS : 32 Total production : 45 Input modules:180  Should be able to avoid re-work during ATLAS life span Module cost: see handout

3. Uli Schäfer 3 QA / acceptance tests PCB manufacturer and assembly company are two branches of the same company Manufacturer operates to ISO9001-2000 All bare PCBs will be electronically tested and impedance checked using test coupons BGAs will be X-rayed Assembled boards will be inspected (AOI: Automated Optical Inspection) In Mainz: Modules will undergo visual inspection upon arrival Modules will be JTAG boundary scanned and modules failing will be returned to the manufacturer Due to the use of scannable buffers and scannable de-serialisers a very large fraction of nets will be covered by the scan Scannable modules are main board and input modules Low JTAG coverage on control module No re-work facility is available in Mainz

4. Uli Schäfer 4 Module tests (JEM, input module) Check incoming supplies for shorts (5V/3.3V) Check secondary supplies for shorts (JEM only) Power up module Check supply voltage indicators Measure secondary supply voltages (JEM only) Mount test adapters Mount 4 previously tested input modules (JEM only) Connect JTAG cables Perform boundary scan Perform basic LVDS test (IM only) Check DCI signal shape with an oscilloscope (1 per bank) Set serial number via solder links JEM: Mount daughter modules (RM,CM, TTCDec) Mount front panel and strengthening bars Insert compact flash card Check DONE indicators Check main clock on front panel connector with an oscilloscope Module ready for crate tests…

5. Uli Schäfer 5 Module tests Readout module: Mount temperature sensor Check power supply planes for shorts Control module Check power supply planes for shorts Mount on test card Connect JTAG cable Perform boundary scan Connect Xilinx parallel cable Flash the CPLD Connect serial cable Download CAN code

6. Uli Schäfer 6 Module acceptance tests : equipment JTAG Power supply 5V/5A, 3.3V/5A (scannable de-serialisers !) JTAG tester (JTAG technologies) 2-port Test adapters: Input module (test motherboard, including basic LVDS test) Control module (test motherboard) Main board Backplane Control module Readout module TTCdec module There won‘t be an adapter plugged into the input sockets, working input modules will be used CPLD and CAN programming Power supply 5V/5A, 3.3V/5A (or in crate) PC with Xilinx parallel cable & software, serial cable and Fujitsu software