1. 1 Status of Validation Board, Selection Board and L0DU Patrick Robbe, LAL Orsay, 19 Dec 2006

2. 2 Trigger Validation Board (1) 4 prototype boards already produced and used in common tests. All final PCBs produced. 5 (out of 28) boards assembled (preserie) and now under test: –Main signals have been verified on one of these boards, –JTAG test bench under development If no problem found, assembly of remaining boards (serie) will be launched week 4 (End of January 2007).

3. 3 Trigger Validation Board (2) Firmware status: –HCAL L0 trigger algorithm checked during last common test in building 156: correct handling of HCAL inputs + implementation of LUTs for ECAL energy + correct output to Selection Board. –Minor problems identified: BCId Reset: a new GLUE (Specs Interface) firmware version has been sent to Cyril by Daniel. Bit errors observed in input RAMs: related to firmware timings (worst case timing = 40 MHz). New physical synthesis tool used (from Magma company): increase worst case timing to 60 MHz. –ECAL algorithm only very quickly looked at. –New firmware needed for preserie boards (signals controling optical mezzanines distributed among 2 FPGAs).

4. 4 Trigger Validation Board (3) Software Status: –Software under CAT allows to access all functionalities of the board: Input and output spy RAMs Loading of LUT Automatic scan of sampling clock edge for serialized input channels Masking of individual channels Future tests –Tests planned in February to check HCAL path and completely debug ECAL path, using pre-series boards and CROC v3. –Validation board at LAL will be loaded with latest firmwares to run the usual routine tests of the trigger part of the ECAL/HCAL FE Boards.

5. 5 Selection Board (1) 1 prototype board available (used in common tests) 2 (out of 8) boards produced and currently under test (preserie) Entire production available end of February

6. 6 Selection Board (2) Firmware Status: –During last common tests, check that the input from the validation board are read with the correct format and that it can be synchronized. –Communication with L0DU was also checked in a previous test. –Further tests needed to check that the algorithm is working as expected and that the output format is correct. Tests foreseen at CERN in February.

7. 7 Selection Board (3) Software Status: –“Command line” software available to configure board (Credit Card PC) –Integration with PVSS under work TELL1: –All Selection Boards send their input data to 2 TELL1s. –Development of firmware for these TELL1 is Bologna responsibility. –Work to start soon.

8. 8 L0DU The L0DU board is ready for commissioning tests. A first test in the barrack with L0 Muon and ODIN+DAQ is foreseen beginning of February. Final firmware version is available. If necessary, a test with the Selection Board could be planned before March test.

9. 9 Trigger Cabling in Barrack All optical fibers will be received at CERN this week for the L0 Calo in the barrack (input and output links of the Selection Board). Cabling should be exercised rapidly to check the fiber lengths.

10. 10 Selection and L0DU Racks in D3 barrack 11 m link

11. 11 Selection Rack 3.5 m link