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Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.

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Presentation on theme: "Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans."— Presentation transcript:

1 Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans

2 Uli Schäfer 2 Modular design, largely identical to JEM 1.1 : 4 input modules (IM) TTCdec module Control Module (CM) CAN VME control Fan-out of configuration lines G-link readout module (RM) Noise issue on JEM1.1 Widen merger and FIO buses Use external Vref on jet processor (XC2V3000) JEM1.2

3 Uli Schäfer 3 Daughter modules, some remarks TTCdec PLL is required for clock fan-out with non-PLLed buffers Input module had design iteration to add Vcc sensing via SMB bus, otherwise identical. Input1.0 and Input1.1 can both be used on all JEM1.x iterations. RDTP unchanged, therefore all JEM1.x are identical FIO sources. Readout module is the one that has been successfully used during the last few RAL tests, no modification required Final version of control module is currently being designed, add CAN.

4 Uli Schäfer 4 JEM status 4 JEM 1.0 main boards available 3 are fully working, 1 has short on TTCdec module connector (re-work possible) 1 JEM 1.1 main board, ok, except some LVDS links (re-work possible) 1 JEM 1.2 main board, so far fully working, 3 tracks needed to be fixed (1 design error, 1 PCB error, 1 assembly problem (due to re-work: upgrade XC2V2000  XC2V3000)), minor problems with VME timing, fixed (?) 5 JEMs currently populated with input modules V1.0 5 new G-link modules available Assembled by Bruno (SAMTEC connectors difficult to assemble by hand) So far 3 fully working 0-version of control module No CAN No VME CPLD Sum processor configuring from flash (ACE, working on JEM1.1, 1.2), all others via VME  JEM1s working (standard tests) Firmware (sum, input) stable (readout tested with 9U RODs)

5 Uli Schäfer 5 JEM 1.x status : tests Apart from CMM/FIO noise issue all JEM 1.x versions are considered equal and compatible JEM tests done in Mainz, at RAL and CERN test beam So far up to 4 JEMs in a 9U crate allowing for FIO tests either direction, along with VMM, TCM, CMM (and CPMs!) External data sources for LVDS : 1 DSS 16-channel (MZ) Several DSS (RAL) LSM (MZ, RAL) PPM (RAL, CERN - 4 channels) External data sinks for Merger signals : 2 CMMs (RAL) Readout path: Complete ROS (RAL, CERN) w. 6U and 9U ROD DSS-based G-link tester (MZ)

6 Uli Schäfer 6 JEM status : tests System tests at RAL: (from June 2004) DSS  JEM  crate CMM  system CMM  ROD  ROS  ROD  ROS Comparing readout data against simulation. Data taken up to 5 slices of JEM DAQ data. Trigger rate up to 60kHz, 4*10 6 events analysed, no errors observed on JEM readout. Interface tests: LVDS inputs, merger outputs, FIO, readout links BER measured, no errors in 10 13 (CMM,FIO), 10 14 (ROD), 10 15 bits (LVDS)

7 Uli Schäfer 7 JEM tests Oct. / Nov. 2005 4 JEMs, including JEM1.2, 2CMMs, 9U ROD (+6U) 1 JEM fed by LSM, plus others in playback mode Generate 2 jets plus a lot of noise Short runs with readout of JEM and CMMs enabled Overnight runs with just summary readout through CMMs  Error free operation Week Nov.14 :  repeat measurements with higher statistics plus more stressful patterns  Use PPM as a data source  Dedicated high statistics tests for FIO signals (firmware based pattern detection).  Read out a minimum of 3 JEMs (test JEM1.2 FIOs either direction in one go )!

8 Uli Schäfer 8 FIO signals JEM1.1 All data latched into the jet processor on a common clock edge. Sweep TTCrx delay setting, 104ps steps. Measure data errors on each channel : 10 bits, 5 signal lines  6.5ns error-free data window. Never ever seen any FIO bit errors. But: noise rather high (CMOS thresholds are at 35% / 65% of 1.5V Vcc) Some of the signal distortion is due to cross talk.

9 Uli Schäfer 9 Noise JEM1.1  JEM1.2 For FIOs use HSTL sensing : +/- 100 mV thresholds rather than +/- 225 mV  works For merger lines widening the data buses is only measure to reduce cross talk  works (see below)  Noise issue has been resolved on JEM1.2 ! JMM, 1.1JMM, 1.2 FIO, 1.2 320 mV 200mV/div100mV/div

10 Uli Schäfer 10 Plans Conclude pre-PRR tests in week Nov. 14 Update documentation Further design work required Finalise control module (CAN / VME / configuration) JTAG test adapters PRR ~ Nov. 30 ? Order components / PCB / assembly early December 4 (?) pre-production to be made within 6 weeks 2 weeks test ( full crate test : 1 week test session at RAL) Full production immediately after, if pre-production successful Due to lower cost we will try and start production of daughter modules required on pre-production JEMs before PRR !  Production JEMs available for test mid March 2006 !!!! Lead time for FPGAs !!!!

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