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TEL62 update Franco Spinella INFN-Pisa 28/3/2012 CERN- TDAQ WG.

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Presentation on theme: "TEL62 update Franco Spinella INFN-Pisa 28/3/2012 CERN- TDAQ WG."— Presentation transcript:

1 TEL62 update Franco Spinella INFN-Pisa 28/3/2012 CERN- TDAQ WG

2 TEL62  News after last meeting: Final acceptance tests on V1 Differences between V1 and V2 Submission of V2 for manufacturing -> pre- production planning Components procurement Issue on optical receiver Mechanical parts Firmware (Bruno’s talk) Testing for V2 pre-production and preparation for final production in 2013.

3 Final tests on V1  Missing TEL 62 (v1) tests: GBIT interface was fully tested (M.S.) Data written in an SL FIFO through ECS and then sent to a PC through UDP ethernet packets. DDR2 high intensity tests. Altera provided test firmware was reading/writing one DDR2 with no errors. TDCB interface (Bruno) Data from TDC were received from a FIFO in the PP and readout through ECS V1 is completely tested! Minimal modifications for V2!!!

4  Some minor mistakes corrected  RJ11 for choke/error becomes RJ45  Side effect: 2 spare LVDS lines (I/O jumper selectable)  TTCRx optical receiver: supports both new and old component 4/10 TDAQ WG V1 -> V2 NEW GERBER FILES FROM PASCAL READY SINCE end of February

5 V2 pre-production  13 TEL62 V2 boards are needed for the dry-run  Time table:  V2 gerber files were submitted to the manufacturing company beginning of March. We want to assemble a first board, test it and later-on the remaining 12 PCBs (15) already produced. The first board will be assembled next week. Should be in Pisa just after Easter (April 10) Acceptance tests: hopefully 10 working days Production of 12 additional cards : 2 weeks (beginning of May, but some components are missing) Test of the 12 cards before releasing…

6 Components procurement  We bought the parts for 10 board, one V1 and 9 V2. Actual request is for 13 V2 -> we miss some parts for 4 cards. “Main” parts already bought -> should be solved with an additional order from Digikey.  Elena is following all the aspects of the procurement.  We are trying to buy all the parts subject to obsolescence for the full production: DDR2 FPGAs DC/DC QDR OPTICAL RECEIVERS … ALMOST EVERYTHING …

7 Optical receiver  Old optical receivers used by LHC TRR1B43… are no more available  CERN has found a replacement: Ficer 155-141210-012  TEL62 V2 supports both old and new receiver  CERN has ordered many of them, some for us, but Ficer sent the wrong ones …155-280711-048 Similar number but different pinout …  Ficer will replace the wrong ones but in the mean while we are without …  But we have an hidden bunch of old ones..

8 Mechanical parts  Mechanical components:  3 different TDCB support spacers are needed Already designed and prototype under production. We plan to use a plastic material (Delrin or similar)  The front panel is already designed but quite critical. prototype production after the spacers.

9 Firmware  See Bruno’s talk …  We are all involved in individual tasks … Marco is working on the GBIT interface and ECS Elena is working on the QDR controller Bruno on the TDCB interface on the PP I’m working on the DDR2 interface and TDCB data handling Work in progress …

10 Testing for V2 pre-production and preparation for final production in 2013.  We have developed special firmware sections to test all the main components of the TEL62. These will remain in the final firmware for real time hardware debugging.  So the testing of TEL62 V2 should be fast …but … In V1 there were an FPGA pin and some pins of a connector badly soldered => many days to debug … If this happens in some of the V2 boards this could be a serious issue …  A possible solution would be developing a set of JTAG boundary scan vectors to completely test the board connectivity  Andrea Salamon is working on this … some hardware is needed  Probably we can survive without the BST for the pre-production but it is a real need for next year mass production. BST DDR SODIMM TESTER


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