1. Welcome to TEL62 workshop M. Sozzi Pisa - January 30/31, 2014

2. Share (some of) the information to build a community of expert users Speed up bug-hunting with more users Provide a brain-storming introduction to initialize new contributors to the firmware As an aside: provide information to our LHCb colleagues for using in novel ways the boards they acquired Collect desiderata and suggestions for improvement (beware: after this meeting you might be asked to contribute yourself !) Push “TEL62” up on google search results The goals

3. Today: dump on you more information than you might possibly stand Tomorrow: try to give you a flavour of what it all means in practice Anytime: ask questions and start discussion The plan

4. But… There’s a huge difference in expertise and previous knowledge in the audience… Trying to find a balance between and also depends on you…

5. The agenda

6. Do not try to memorize or take note of details Just focus on the concepts Some things might become clearer in later talks Not everything might suit your needs The project is not at all complete yet All you will learn is how things are intended to be (not necessarily how they are today) Please note

7. Documentation We are making an effort to provide comprehensive documentation but we need your (newcomers) help: If you struggle with something, chances are it is not documented well enough: please, do a favor to your colleagues and let us know!

8. NA62 Twiki pages (NA62 collaborators only) https://twiki.cern.ch/twiki/bin/viewauth/NA62/TdaqSystem Manuals (all continuously evolving): TDCB Manual TEL62 (firmware) Manual Data formats document TDSPY Manual Papers Documentation

12. TELL1 EPFL Lausanne 2002-2008 TEL62 INFN Pisa 2010-2013 A-Rx O-Rx TDCB GbE

13. TELL1 to TEL62 Stratix I (25K LE) to Stratix III (200K LE) DDR (256 Mbit) to DDR2 (16 Gbit) 1 x 32-bit PP-SL bus to 2 32-bit PP-SL buses 2 x 16-bit buses between neighbouring PPs AUX connector with 2 x 16-bit buses (Inter-TEL) Different firmware EPROMs New power distribution scheme Internal note NA62-10-06

14. Customization 1.Use the TEL62 hardware with no mezzanines (i.e. develop your own input and or output daughter-cards) 2.Use some of the existing TELL1/TEL62 mezzanines 3.Use the software libraries and/or control program 4.Use the general-purpose common NA62 firmware (SL) 5.Use the TDCB-specific NA62 firmware (PP) 6.Use NA62 subdetector-specific firmware More NA62ishLess NA62ish

15. Reminder for LHC people NA62 is a fixed-target SPS experiment with a machine-driven beam spill-based time structure: Variable, a few s beam spill and a (longer) interspill with an overall period below 1m StartOfBurst – EndOfBurst No bunch crossing, different use of TTC

16. TDCB TEL62 GbE Front End LTUTTCex RX-LKr TEL62 TX LKr Front End RX TEL62 GbE L0TP Inter TEL The picture

17. Some jargon CCPC (or ECS): Credit-Card PC DDR: Double Data Rate dynamic RAM EOB: End Of Burst EPCS: Firmware EPROM FPGA: Field Programmable Gate Array GbE: Quad Gigabit Ethernet mezzanine HPTDC: High-Performance TDC chip JBC: JAM Byte Code (firmware file) I2C: Inter-Integrated Circuit serial bus JTAG: Joint Test Action Group serial bus L0TP: L0 Trigger Processor LTU: Local Trigger Unit MAC: Media Access Controller chip MEP/MTP: Multi-Event/Multi-Trigger packet PHY: Physical layer network controller chip PP: Pre-Processing FPGA QDR: Quad Data Rate dynamic RAM SL:Sync-Link FPGA SOB: Start Of Burst SOF: SRAM Object File (firmware file) SVN: Subversion version control tool TDCB: TDC board TDCC: TDC controller FPGA TTC: Trigger Timing and Control system TTCex: TTC encoder module UDP: User Datagram Protocol VHDL: VHSIC Hardware Description Language