The Processor Lecture 3.2: Building a Datapath with Control Be aware that this first part of new chapter 4 is review for this class, so doesn’t go into detail. If your students are learning computer organization for the first time, this set of slides needs to be expanded greatly.

Learning Objectives Describe what happens in fetching an instruction Describe what happens in decoding an instruction Describe the execution of following instructions R-type instructions Load/store instructions Branch and jump instructions Explain the purposes of various control signals

Coverage Chapter 4.3: Building a Datapath Chapter 4.4, Page 259-264: Adding Control

Building a Datapath Chapter 4.3

Fetching Instructions Fetching instructions involves reading the instruction from the Instruction Memory updating the PC value to be the address of the next (sequential) instruction Read Address Instruction Memory Add PC 4 clock Fetch PC = PC+4 Decode Exec PC is updated every clock cycle, so it does not need an explicit write control signal

Decoding Instructions Decoding instructions involves sending the fetched instruction’s opcode field bits to the control unit Fetch PC = PC+4 Decode Exec Control Unit Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 Instruction reading two values from the Register File Register File addresses are contained in the instruction

Executing R Format Operations R format operations (add, sub, slt, and, or) perform operation (op and funct) on values in rs and rt store the result back into the Register File (into location rd) R-type: 31 25 20 15 5 op rs rt rd funct shamt 10 Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 ALU overflow zero ALU control RegWrite Fetch PC = PC+4 Decode Exec Since writes to the register file are edge-triggered, we can legally read and write the same register within a clock cycle – the read will get the value written in an earlier clock cycle, which the value written will be available to a read in a subsequent cycle. Note that Register File is not written every cycle (e.g., sw), so we need an explicit write control signal for the Register File

Executing Store Operations Store operations involve compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction store value (read from the Register File during decode) written to the Data Memory Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 ALU overflow zero ALU control Data Memory Address Read Data Sign Extend MemWrite Note there are separate read and write controls to the memory – only one of which may be asserted on any given clock cycle. The memory unit needs a read signal, since, unlike the register file, reading the value of an invalid address can cause problems as we will see later. (Standard memory chips actually have a write enable signal that is used for writes.) 16 32

Executing Load Operations Load operations involve compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction load value (read from the Data Memory) written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Data 2 ALU overflow zero ALU control RegWrite Data Memory Address Read Data Sign Extend MemRead Note there are separate read and write controls to the memory – only one of which may be asserted on any given clock cycle. The memory unit needs a read signal, since, unlike the register file, reading the value of an invalid address can cause problems as we will see later. (Standard memory chips actually have a write enable signal that is used for writes.) 16 32

Executing Branch Operations Branch operations involve compare the operands read from the Register File during decode for equality (zero ALU output) compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr Add Branch target address Add 4 Shift left 2 ALU control PC zero (to branch control logic) Read Addr 1 Read Data 1 Register File Read Addr 2 Instruction ALU Write Addr Read Data 2 Write Data Sign Extend 16 32

Executing Jump Operations Jump operation involves replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Add 4 4 Jump address Instruction Memory Shift left 2 The up 4 bits of the PC+4 and the 28 bits are concatenated together to form the 32-bit address for instruction memory. 28 Read Address PC Instruction 26

Creating a Single Datapath from the Parts Assemble the datapath segments and add control lines and multiplexors as needed Single cycle design – fetch, decode and execute each instruction in one clock cycle no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) multiplexors needed at the input of shared elements with control lines to do the selection write signals to control writing to the Register File and Data Memory Cycle time is determined by the length of the longest path

Fetch, Register, and Memory Access Portions MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Data 1 Data 2 ALU ovf zero ALU control RegWrite Data Read Data MemWrite MemRead Sign Extend 16 32 ALUSrc zero flag of ALU ‘1’: result is zero ‘0’: result is not zero

Full Datapath (without Jump) This diagram is provided by the textbook. There are places that are not inaccurate. The write_register input of the register file needs a multiplexor. The “Zero flag” from the ALU does not point to the Data Memory.

Adding Control Units Chapter 4.4, page 259

Adding the Control Selecting the operations to perform (ALU, Register File and Memory read/write) Controlling the flow of data (multiplexor inputs) 31 25 20 15 10 5 R-type: op rs rt rd shamt funct Observations op field always in bits 31-26 addr. of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16) in lw and sw rs is the base register addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions offset for beq, lw, and sw always in bits 15-0 31 25 20 15 I-Type: op rs rt address offset J-type: 31 25 op target address

The Main Control Unit Control signals derived from instruction rs rt R-type rs rt rd shamt funct 31:26 5:0 25:21 20:16 15:11 10:6 Load/ Store 35 or 43 rs rt address 31:26 25:21 20:16 15:0 4 rs rt address 31:26 25:21 20:16 15:0 Branch opcode always read always read write for R-type and load sign-extend

Single Cycle Datapath with Control Unit (w/o jump) Add Add 1 4 Shift left 2 PCSrc ALUOp Branch MemRead Instr[31-26] Control Unit MemtoReg MemWrite ALUSrc RegDst RegWrite ovf Instr[25-21] Read Addr 1 Instruction Memory Read Data 1 Address Register File Instr[20-16] zero Read Addr 2 Data Memory Read Address PC Instr[31-0] Read Data 1 ALU Write Addr Read Data 2 1 Write Data Instr[15 -11] Write Data 1 Instr[15-0] Sign Extend ALU control 16 32 Instr[5-0]

Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Data 1 Data 2 ALU ovf zero RegWrite Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 PCSrc RegDst control 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Jump Instr[25-0] 26 PC+4 [31-28] 28

ALU Control ALU used for Load/Store: Function = add Branch: Function = subtract R-type: Function depends on funct field ALU control (output) Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set-on-less-than The ALU control has 4-bits, which can specify up to 16 different functions. We only discuss 5 functions here.

ALU Control Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control opcode ALUOp Operation funct ALU function ALU control lw 00 load word XXXXXX add 0010 sw store word beq 01 branch equal subtract 0110 R-type 10 100000 100010 AND 100100 0000 OR 100101 0001 set-on-less-than 101010 0111