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Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

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Presentation on theme: "Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]"— Presentation transcript:

1 Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]

2 Abstract Implementation View

3 Register Transfer Language  RTL gives the meaning of the instructions  All start by fetching the instruction {op, rs, rt, rd, shamt, funct} = MEM[ PC ] {op, rs, rt, Imm16} = MEM[ PC ] inst Register Transfers ADDUR[rd] = R[rs] + R[rt];PC = PC + 4 SUBUR[rd] = R[rs] – R[rt];PC = PC + 4 ORIR[rt] = R[rs] | zero_ext(Imm16); PC = PC + 4 LOADR[rt] = MEM[ R[rs] + sign_ext(Imm16)]; PC = PC + 4 STOREMEM[ R[rs] + sign_ext(Imm16) ] = R[rt]; PC = PC + 4 BEQ if ( R[rs] == R[rt] ) then PC = PC + 4 + (sign_ext(Imm16) || 00) else PC = PC + 4

4  We're ready to look at an implementation of the MIPS  Simplified to contain only: l memory-reference instructions: lw, sw l arithmetic-logical instructions: add, addu, sub, subu, and, or, xor, nor, slt, sltu l arithmetic-logical immediate instructions: addi, addiu, andi, ori, xori, slti, sltiu l control flow instructions: beq, j  Generic implementation: l use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) l decode the instruction (and read registers) l execute the instruction The Processor: Datapath & Control Fetch PC = PC+4 DecodeExec

5 Abstract Implementation View  Two types of functional units: l elements that operate on data values (combinational) l elements that contain state (sequential)  Single cycle operation  Split memory (Harvard) model - one memory for instructions and one for data AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

6 Clocking Methodologies  Clocking methodology defines when signals can be read and when they can be written falling (negative) edge rising (positive) edge clock cycle clock rate = 1/(clock cycle) e.g., 10 nsec clock cycle = 100 MHz clock rate 1 nsec clock cycle = 1 GHz clock rate

7 Clocking Methodologies  Typical execution l read contents of state elements l send values through combinational logic l write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle  Assumes state elements are written on every clock cycle; if not, need explicit write control signal l write occurs only when both the write control is asserted and the clock edge occurs

8 Fetching Instructions  Fetching instructions involves l reading the instruction from the Instruction Memory l updating the PC value to be the address of the next (sequential) instruction Read Address Instruction Memory Add PC 4 l PC is updated every clock cycle, so it does not need an explicit write control signal l Instruction Memory is read every clock cycle, so it doesn’t need an explicit read control signal Fetch PC = PC+4 DecodeExec clock

9 Decoding Instructions  Decoding instructions involves l sending the fetched instruction’s opcode and function field bits to the control unit and Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit l reading two values from the Register File -Register File addresses are contained in the instruction Fetch PC = PC+4 DecodeExec

10  Note that both RegFile read ports are active for all instructions during the Decode cycle using the rs and rt instruction field addresses l Since haven’t decoded the instruction yet, don’t know what the instruction is ! l Just in case the instruction uses values from the RegFile do “work ahead” by reading the two source operands Which instructions do make use of the RegFile values?  Also, all instructions (except j ) use the ALU after reading the registers Reading Registers “Just in Case”

11 Executing R Format Operations  R format operations ( add, sub, slt, and, or ) l perform operation (op and funct) on values in rs and rt l store the result back into the Register File (into location rd) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: 3125201550 oprsrtrdfunctshamt 10 l Note that Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File Fetch PC = PC+4 DecodeExec

12  Remember the R format instruction slt slt $t0, $s0, $s1 # if $s0 < $s1 # then $t0 = 1 # else $t0 = 0 2 Consider the slt Instruction l Where does the 1 (or 0) come from to store into $t0 in the Register File at the end of the execute cycle? Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite

13 Executing Load and Store Operations  Load and store operations have to l compute a memory address by adding the base register (in rs) to the 16-bit signed offset field in the instruction -base register was read from the Register File during decode -offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value l store value, read from the Register File during decode, must be written to the Data Memory l load value, read from the Data Memory, must be stored in the Register File I-Type: oprsrt address offset 312520150

14 Executing Load and Store Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead

15 Executing Load and Store Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

16 Executing Load and Store Operations Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead

17 Executing Load and Store Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

18 Executing Branch Operations  Branch operations have to l compare the operands read from the Register File during decode (rs and rt values) for equality ( zero ALU output) l compute the branch target address by adding the updated PC to the sign extended16-bit signed offset field in the instruction -“base register” is the updated PC -offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value and then shifted left 2 bits to turn it into a word address I-Type: oprsrt address offset 312520150

19 Executing Branch Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

20 Executing Branch Operations, con’t Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

21 Executing Jump Operations  Jump operations have to l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28 J-Type: op 31250 jump target address

22 Creating a Single Datapath from the Parts  Assemble the datapath elements, add control lines as needed, and design the control path  Fetch, decode and execute each instructions in one clock cycle – single cycle design l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory) l to share datapath elements between two different instruction classes will need multiplexors at the input of the shared elements with control lines to do the selection  Cycle time is determined by length of the longest path

23 Fetch, R, and Memory Access Portions Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632

24 Multiplexor Insertion MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

25 Adding the Branch Portion Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc

26 Basic Implementation of MIPS - Datapath + Control

27 Review: A Simple MIPS Datapath Design Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero Data Memory Address Write Data Read Data Sign Extend 1632 Read Address Instruction Memory Add PC 4 Shift left 2 Add

28 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Information comes from the 32 bits of the instruction I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10  Observations l op field always in bits 31-26 l addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16) l base register for lw and sw always in rs (bits 25-21) l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0

29 (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc 1 0 RegDst 0 1 1 0 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]

30 (Almost) Complete Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

31 Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R- type 000000 lw 100011 sw 101011 beq 000100  Completely determined by the instruction opcode field l Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

32 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch zero

33 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

34 Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

35 Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

36 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

37 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

38 Review: A Simple MIPS Datapath Design Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Read Address Instruction Memory Add PC 4 Shift left 2 Add PCSrc

39 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs)  Information comes from the 32 bits of the instruction I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10  Observations l op field always in bits 31-26 l addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16) l base register for lw and sw always in rs (bits 25-21) l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0

40 (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc 1 0 RegDst 0 1 1 0 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11]

41 (Almost) Complete Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

42 Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R- type 000000 lw 100011 sw 101011 beq 000100  Completely determined by the instruction opcode field l Note that a multiplexor whose control input is 0 has a definite action, even if it is not used in performing the operation

43 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch zero

44 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

45 Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

46 Store Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

47 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

48 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

49 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

50 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

51 Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOp R-type 000000 100100010 lw 100011 011110000 sw 101011 X1X001000 beq 000100 X0X000101  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

52 Control Unit Logic  From the truth table can design the Main Control logic Instr[31] Instr[30] Instr[29] Instr[28] Instr[27] Instr[26] R-type lwswbeq RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp 1 ALUOp 0

53 Review: Handling Jump Operations  Jump operation have to l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28 J-Type: opjump target address 310

54 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

55 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

56 Main Control Unit InstrRegDstALUSrcMemRegRegWrMemRdMemWrBranchALUOpJump R-type 000000 1001000100 lw 100011 0111100000 sw 101011 X1X0010000 beq 000100 X0X0001010 j 000010 XXX000XXX1  Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

57 Single Cycle Implementation Cycle Time  Unfortunately, though simple, the single cycle approach is not used because it is very slow  Clock cycle must have the same length for every instruction  What is the longest path (slowest instruction)?

58 Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instr l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  It is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

59 Where We are Headed  Another approach l use a “smaller” cycle time l have different instructions take different numbers of cycles l a “multicycle” datapath Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout

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