1. CS/COE0447 Computer Organization & Assembly Language
Chapter 5
Part 1

2. A Simple MIPS Memory reference instructions
lw (load word) and sw (store word)
Arithmetic-logical instructions
add, sub, and, or, and slt
Control-transfer instructions
beq (branch if equal)
j (unconditional jump)

3. An Abstract Implementation (fig 5.1)
Combinational logic
ALU, adder
Sequential logic
Register file, instruction memory, data memory

4. Instruction Execution
lw (load word)
Fetch instruction
Read a base register
Sign-extend the immediate offset
Add two values to get address
Access data memory with the address
Store the memory data to the destination register

5. Instruction Execution, cont’d
add
Fetch instruction
Read two source registers
Add two values
Store the result to the destination register

6. Instruction Execution, cont’dj
Fetch instruction
Take the 26-bit immediate field
Shift left by 2 (to make 28-bit immediate)
Get 4 bits from the current PC and attach to the left of the immediate
Assign the value to PC

7. Components: Building a Datapath
ALU – Arithmetic (add,sub) and logic (and, or) Unit
Memory
Instruction memory to supply instructions
Data memory (loading and storing) PC
Essentially a register
Update logic (increment/jump address)

8. Components, cont’d Register file Immediate Support for branch and jump
32 32-bit registers
2 read ports, one write port
Immediate
Sometimes instruction contains immediate
We may sign-extend it
Support for branch and jump

9. Building Blocks (figs 5.7-5.8)

10. from which instruction
Instruction Fetch
Instruction width
is 4 bytes!
PC keeps the current
memory address
from which instruction
is fetched
Instruction memory
here is read-only!

11. Branch Datapath (fig. 5.9)

12. Memory + R-Instructions (fig 5.10)
E.G: lw $t0,8($t1)
Load data
from memory
Imm. offset
for address
To be in
a register!

13. Memory + R-Instructions (fig 5.10)
E.G: sw $t0,8($t1)

14. Memory + R-Instructions (fig 5.10)
E.G: add $t0,$t1,$t2; MUX selections are reversed

15. Datapath so far (fig 5.11)
j not considered
so far!

16. Instruction Format

17. More Elaborated Design (fig 5.15)
Write register #
selection
ALU control bits
from I[5:0]

18. A First Look at Control (fig 5.17)

19. Control Signals Overview
RegDst: which instr. field to use for dst. register specifier?
instruction[20:16] vs. instruction[15:11]
ALUSrc: which one to use for ALU src 2?
immediate vs. register read port 2
MemtoReg: is it memory load?
RegWrite: update register?
MemRead: read memory?
MemWrite: write to memory?
Branch: is it a branch?
ALUop: what type of ALU operation?

20. Generic Control Sequence
For each fetched instruction
(decoding)
Select two registers to read from register file
Select the 2nd ALU input
Select ALU operation
Select if data memory is to be accessed
Select if register file is updated
Select what to assign to PC