2. Datapath and Control AddressInstruction Memory Write Data Reg Addr Register File ALU Data Memory Address Write Data Read Data PC Read Data Read Data

3. Executing Load and Store Operations  Load and store operations compute a memory address by adding the base register (in rs ) to the 16-bit signed offset field in the instruction  The 32 bits in the base register were read from the Register File during decode  The offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value I-Type: oprsrt address offset 312520150

4. Data Memory Address Write Data Read Data MemWrite MemRead 1632 Sign Extend 16-bit offset RegWrite Read Addr 1 zero ALU overflow Write Data Instruction Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU control  sw - value read from the Register File during decode must be written to the Data Memory  lw - value read from the Data Memory must be stored in the Register File Executing Load and Store Operations

5. Executing Branch Operations  Branch operations have to compare the operands read from the Register File during decode ( rs and rt values) for equality ( zero ALU output is asserted)  compute the branch target address by adding the updated PC to the sign extended 16-bit signed offset field in the instruction  offset value in the low order 16 bits of the instruction must be sign extended to create a 32-bit signed value and then shifted left 2 bits to turn it into a word address I-Type: oprsrt address offset 312520150

6. Executing Branch Operations RegWrite Read Addr 1 zero ALU overflow Write Data Instruction Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU control (to branch control logic -take branch if zero line is high) Add Branch target address Shift left 2 Add 4 PC PC + 4 (perform a subtraction) 3216 16-bit offset Sign Extend

7. Executing Jump Operations  Jump operations have to replace the lower 28 bits of the PC+4 with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 264 Shift left 2 28 Jump address J-Type: op 31250 jump target address

8. Creating a Single Datapath from the Parts  We need to assemble the datapath segments, add control lines as needed, and design the control path  Fetch, decode and execute each instruction in one clock cycle – single cycle design. Cycle time is determined by length of the longest path  No datapath resource can be used more than once per instruction, so some must be duplicated (that is why we have a separate Instruction Memory and Data Memory)  To share datapath elements between different instruction classes will need multiplexors at the input of the shared elements  Need control lines to do the selection of inputs

9. Fetch, R, and Memory Access Portions Read Address Instruction Memory Add PC 4 RegWrite ovf zero ALU control ALU Data Memory Address Write Data Read Data MemWrite MemRead lw RR Sign Extend 1632 lw / sw Register File Write Data Read Addr 1 Read Addr 2 Write Addr Read Data 1 Read Data 2

10. Multiplexor Insertion MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

11. Adding the Branch Portion Add 4 Shift left 2 Add Read Address Instruction Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc R lw / sw R lw PCSrc Branch not taken, R, lw /sw

12.  We wait for everything to settle down - ALU might not produce “right answer” right away  Cycle time determined by length of the longest path  Split memory (Harvard) model - single cycle operation  Simplified to contain only the instructions: lw, sw, add, sub, and, or, slt, beq.  Sequential components (PC, RegFile, Memory) are edge triggered - state elements are written on every clock cycle; if not, need explicit write control signal  write occurs only when both the write control is asserted and the clock edge occurs Datapath - review

13. Single cycle datapath  Observations - op field always in bits 31-26  address of the two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16)  address of register to be written is in one of two places – in rt (bits 20-16) for lw ; in rd (bits 15-11) for R - type instructions  base register for lw and sw always in rs (bits 25-21)  offset for beq, lw, and sw always in bits 15-0 I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10

14. (Almost) Complete Single Cycle Datapath Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr ALU ovf zero Data Memory Address Write Data Read Data MemWrite MemRead Register File Read Data 1 Read Data 2 RegWrite Sign Extend 1632 Shift left 2 Add RegDst 0 1 ALUSrc 0 1 MemtoReg 1 0 PCSrc 1 0 ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[ 15 -11]