Processor II CPSC 321 Andreas Klappenecker. Midterm 1 Tuesday, October 5 Thursday, October 7 Advantage: less material Disadvantage: less preparation time.
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Midterm 1 Tuesday, October 5 Thursday, October 7 Advantage: less material Disadvantage: less preparation time Tuesday, October 12 Advantage: more preparation time Disadvantages: more material, less time for the project.
Administrative Issues Allen Parish will not have a help session this Friday, but again in subsequent Fridays. I will have extra office-hours this Friday, 10:30am-11:30am. There will be no office hours on Tuesday morning (PhD defense).
Today’s Menu The Datapath of the Processor Control
The Processor: Datapath and Control We want to implement portions of MIPS memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq (we will implement j later) We recall the datapaths of these instructions and compose them.
Instruction Word Formats Register format: add, sub, and, or, slt Immediate format: lw, sw, beq Jump format op-code rs rt rd shamt funct op-code rs rt immediate value op-code 26 bit current segment address 6 55 16 6 555 5 6 6 26
Requirements of the Instruction Set Memory Register file PC Sign extender ALU Add 4 to increase PC
Instruction Fetch + PC update The new value PC=PC+4 will be assigned, say, on falling-edge of the clock signal The fetched instruction is used by other parts of the data path
R-Format Instructions Register format op-code rs rt rd shamt funct 6 555 5 6 You can read at any time, but write only when the RegWrite signal is asserted
Timing for One Clock Cycle 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU Clk PC Rs, Rt, Rd, Op, Func Clk-to-Q ALUctr Instruction Memory Access Time Old ValueNew Value RegWr Old ValueNew Value Delay through Control Logic busA, B Register File Access Time Old ValueNew Value busW ALU Delay Old ValueNew Value Old ValueNew Value Old Value Register Write Occurs Here
Control Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $17, $18 Instruction Format: 000000 10001 10010 01000 00000100000 op rs rt rd shamt funct ALU's operation based on instruction type and function code
Datapath for a load and store 1.register access 2.memory access calculation 3.read or write from memory 4.in the case of a load, write into register file
Datapaths for Instruction Fetch, Memory and R-type Instructions xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg xtend ALU result Zero ALU Address RegWrite ALU operation 3 MemRead MemWrite ALUSrc MemtoReg Note the added multiplexor switching between register 2 and sign-extended immediate value
The Branch Instruction beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal <- R[rs] == R[rt]Calculate the branch condition if (Equal)Calculate the next instruction’s address PC <- PC + 4 + ( SignExt(imm16) x 4 ) else PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits
Datapath for a Branch Use ALU to evaluate the branch condition, another adder for branch target = PC + 4 + (sign extended 16 bits)<<2
Marrying Branches with Rest Output of Sign extend goes where? Output of PC adder goes where? (Why do I even ask that?)
Datapath for MIPS instructions Seven control signals
ALU Control For load and store instructions Use ALU to compute memory address by addition (add immediate value) For R-type instructions Perform addition, subtraction, and, or, slt value depends on 6bit function field For beq perform subtraction
ALU Control Logic (Recall ALU) ALU cntrl Function 000and 001or 010add 110subtract 111slt Depending on instruction, the ALU has to perform one of the five operations
Must describe hardware to compute 3-bit ALU control input ALU control bits depend on ALUOp control bits and different functions codes for R-type instructions ALU Control
Datapath for MIPS instructions Note the seven control signals!
Generating Control Signals Opcode field of instruction yields control signals and ALUOp signals