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The Processor: Datapath & Control
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Implementing Instructions
Simplified instruction set memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq (bne), j (jal) Generic implementation: PC to supply instruction address get the instruction from memory use the instruction to decide what to do read registers Majority of instructions use the ALU the actions differ.
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Clocking Methodology 1/2
Edge-triggered methodology values stored in a sequential logic elements are updated only on clock edge Typical execution: read contents of state elements, send values through some combinational logic write results to one or more state elements state element 1 state element 2 Combinational Logic
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Clocking Methodology 2/2
state element Combinational Logic An edge-triggered methodology allows a state element to be read and written in the same clock cycle
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Abstract View of Datapath
Two types of functional units: combinational, e.g. ALU sequential, e.g. registers ALU Address Data Memory Registers Reg. No Instruction PC Add 4 Add
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Datapath Including Control
branch 4 Add Add PC Data Reg. No MemWrite Address Registers Instruction ALU Address Reg. No Instruction Memory zero Data Memory Reg. No RegWrite Data MemRead Control
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Register File Register file 5 Read register number 1 read data 1 32 5
Write register read data 2 32 32 Write data Write
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ALU Symbol & Control ALU Control ALU a b Result Zero Overflow CarryOut
4 ALU control lines Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 slt 1100 NOR ALU 32 a b Result Zero Overflow CarryOut
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Instruction Fetch 4 Add Instruction Memory Address PC Instruction
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R-Type Instructions add rd, rs, rt ALU op rs rt rd shamt funct
6 bits bits bits bits bits bits add rd, rs, rt ALU Control Instruction read register 1 Read register 2 Write register Write data Register file read data 1 data 2 5 32 ALU Zero Overflow CarryOut 4 rs rt rd
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Implementing Load & Stores
op rs rt Imm 6 bits bits bits bits lw rt, index(rs) ALU Address Data Memory Write Data Write Registers Read Reg. 1 MemWrite MemRead RegWrite zero Read Reg. 2 Write Reg. Read Data 1 Data 2 Sign Extend 32 Instruction 16 Immediate ALU Control rs rt rt
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Implementing Branches
op rs rt Imm 6 bits bits bits bits beq rs, rt, Label ALU Write Data Registers Read Reg. 1 RegWrite zero Read Reg. 2 Write Reg. Read Data 1 Data 2 Sign Extend 32 Instruction rs rt 16 Immediate ALU Control Add Shift left 2 PC+4 Branch Target Address To Branch Control Logic
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Building the Datapath Idea: Use multiplexors to stitch them together
rt rd Imm
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Implementing Jump j Label Jump Target Address 26 op Address
6 bits bits j Label PC+4 [31 : 28] Shift left 2 Jump Target Address [27 : 0] 26 rs ALU Control Read Reg. 1 rt Read Data 1 Read Reg. 2 Instruction Registers ALU Write Reg. Read Data 2 Write Data RegWrite
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Complete Datapath with Control
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Control ALU operation is based on instruction type and function code
Control Signals Selecting the operations to perform Controlling the flow of data (via MUX) Read/write enable inputs of memory and register file Information comes from the instruction Example: add $t0, $s0, $s1 op 000000 10000 10001 01000 00000 100000 rs rt rd shamt funct ALU operation is based on instruction type and function code
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ALU Control Example: lw $t0, 100($s2)
What should the ALU do with this instruction? op 100101 10010 01000 rs rt address ALU Control lines Function 0000 AND 0001 OR 0010 add 0110 subtract 0111 set on less than 1100 NOR
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ALU Control Unit ALU performs
addition for loads and stores subtraction for branches (beq) no operation for jumps or the operation is determined by the function field for R-type instructions. ALU Control unit will have the following inputs: 2-bit control field called ALUOp 6-bit function field
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Instruction operation
ALU Control Unit Instruction opcode Instruction operation ALUop Funct field Desired ALU action ALU Control lw Load word 00 xxxxxx add 0010 sw Store word beq Branch equal 01 subtract 0110 R-type Add 10 100000 Subtract 100010 AND 100100 and 0000 OR 100101 or 0001 slt 101010 0111
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Fields of Different Instruction Classes:
Main Control Unit Fields of Different Instruction Classes: rs rt rd shamt funct R-type 31-26 25-21 20-16 15-11 10-6 5-0 35 or 43 rs rt Imm Load or store 31-26 25-21 20-16 15-0 2 address jump 31-26 25-0 4 rs rt Imm branch 31-26 25-21 20-16 15-0
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Datapath with Control Signals
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Effect when de-asserted
Seven Control Signals Signal name Effect when de-asserted Effect when asserted RegDst The destination register number comes from rt. The destination register number comes from rd. RegWrite None Destination register is written with value on Writedata ALUSrc 2nd ALU operand comes from Read_Data_2 2nd ALU operand is the sign extended, lower 16 bit of the instruction PCSrc The PC is replaced by PC + 4 The PC is replaced by the branch target address MemRead Memory is read MemWrite Memory is written MemtoReg The value to the register Writedata input comes from the ALU. The value to the register Writedata input comes from the data memory
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RegDst & RegWrite RegDst RegWrite read register #1 read #1
load read register #1 read #1 read register #2 rt: Ins[20-16] write register Register file rd: Ins[15-11] 1 write data read #1 Write RegDst R-type RegWrite
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ALUSrc RegWrite result ALU ALUSrc read register #1 read #1
Zero write register Register file result ALU read #1 write data 1 Imm: Ins[15-0] sign extend ALUSrc 16 32
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MemtoReg MemtoReg read data 1 Address Data Memory write data
Zero read data 1 Address Data Memory write data MemtoReg From the read data 2 output of Register File To the write data input of Register File
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PCSrc PC Add Add PCSrc zero branch 4 1 sign extend Shift left by 2 32
1 Add PCSrc sign extend Shift left by 2 Imm: Ins[15-0] zero branch 32
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Datapath & Control
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Operation of the Datapath
ALU Op0 ALU Op1 Branch Mem Write Read RegWrite Memto-Reg ALUSrc RegDest Instruction 1 R-format 1 lw 1 X sw 1 X beq Example Flow: beq $s0, $s1, address The instruction is fetched from memory and PC is incremented Read two register values Subtract one from the other, calculate the branch address Use the zero signal to determine which of the addresses is to be used for fetching the next instruction
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Control Function Input or output Signal name R-format lw sw beq Inputs
Op5 1 Op4 Op3 Op2 Op1 Op0 Outputs RegDst x ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALIOp0
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Cycle Time The control logic is combinational
every instruction is executed in one clock cycle Cycle time determined by length of the longest path state element 1 state element 2 Combinational Logic
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Single Cycle Approach Different instructions have different execution times Add: 3 ns Subtract: 3.5 ns Memory access: 10 ns Multiplication: 20 ns In single cycle approach, the slowest instruction determines the clock cycle time. Another approach, divide instruction into smaller parts and execute each in a shorter clock cycle
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Instruction in Datapath
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Functional Units used by the instruction class
Instruction Timings Instruction class Functional Units used by the instruction class R-type Instruction fetch Register access ALU Load word Memory access Store word Branch Jump
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Example Memory access: 200 ps ALU and addition operations: 100 ps Register file access (read or write): 50 ps And assume other parts (multiplexors, control units, etc) have no delay. Instruction mix: 25% loads, 10% stores, 45% ALU ops, 15% branches, 5% jumps Compare two approaches: single fixed clock cycle and multiple clock cycle per instruction, i.e. what is the clock period per instruction and CPI for a fixed cycle what is the nominal clock period and CPI for the multiple cycle approach Execution times?
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