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The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture.

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Presentation on theme: "The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture."— Presentation transcript:

1 The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture

2 The Processor: Datapath and Control We want to implement portions of MIPS memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j We ignore multiply, divide, and other integer and floating point instructions.

3 Abstract, simplified view Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential) Implementation Details

4 Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R-type instruction completion Write-back step Five Execution Steps

5 Instruction Fetch  Use PC to find new instruction  PC = PC + 4, preparing for next instruction

6 Instruction Fetch + PC update

7 R-Format Instructions Register format op: basic operation of instruction funct: variant of instruction rs: first register source operand rt: second register source operand rd: register destination operand shamt: shift amount op-code rs rt rd shamt funct 6 555 5 6

8 Implementing R-Format Instructions  R-Format ALU operations need the register file  and an implementation of the ALU

9 Built using D flip-flops Register File

10 Reading the Register File Multiplexers select the outputs

11 D flip-flop Output changes only on falling clock edge

12 Writing into the Register File log n+1 input bits address n+1 registers Falling edge of clock signal determines when to write

13 Implementing Loads and Stores Register file, ALU, data memory unit, sign extension unit

14 Datapath for a load and store 1. register access 2. memory access calculation 3. read or write from memory 4. in the case of a load, write into register file

15 Datapath for a Branch Use ALU to evaluate the branch condition, another adder for branch target = PC + 4 + (sign extended 16 bits)>>2

16 Summary  Found implementations for R-format instructions  Found implementations for loads and stores  Found implementations for branches  We need to compose these datapaths  Simplicity of the implementations is striking!

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