The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture.
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The Processor 2 Andreas Klappenecker CPSC321 Computer Architecture
The Processor: Datapath and Control We want to implement portions of MIPS memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j We ignore multiply, divide, and other integer and floating point instructions.
Abstract, simplified view Two types of functional units: elements that operate on data values (combinational) elements that contain state (sequential) Implementation Details
Instruction Fetch Instruction Decode and Register Fetch Execution, Memory Address Computation, or Branch Completion Memory Access or R-type instruction completion Write-back step Five Execution Steps
Instruction Fetch Use PC to find new instruction PC = PC + 4, preparing for next instruction
Reading the Register File Multiplexers select the outputs
D flip-flop Output changes only on falling clock edge
Writing into the Register File log n+1 input bits address n+1 registers Falling edge of clock signal determines when to write
Implementing Loads and Stores Register file, ALU, data memory unit, sign extension unit
Datapath for a load and store 1. register access 2. memory access calculation 3. read or write from memory 4. in the case of a load, write into register file
Datapath for a Branch Use ALU to evaluate the branch condition, another adder for branch target = PC + 4 + (sign extended 16 bits)>>2
Summary Found implementations for R-format instructions Found implementations for loads and stores Found implementations for branches We need to compose these datapaths Simplicity of the implementations is striking!