Download presentation
Presentation is loading. Please wait.
1
COMS 361 Computer Organization
Title: MIPS Datapath Date: 12/02/2004 Lecture Number: 26
2
Announcements
3
Review MIPS implementation Subset of the MIPS instruction set
4
Outline MIPS implementation Subset of the MIPS instruction set
Data flow Control
5
The Processor All MIPS instructions use the ALU after reading the registers Why? Memory-reference? Effective address must be computed Arithmetic? Operation execution Control flow? Comparison
6
The Processor Instruction completion differs among classes after using the ALU Memory-reference Access memory write data for a store read data for a load Arithmetic Write the ALU data into a register Control flow May need to modify the address in the PC
7
The Processor Design steps completed Next step:
1) Analyze instruction set => datapath requirements 2) Select set of datapath components and establish clocking methodology Next step: 3) Assemble datapath meeting the requirements
8
Implementation Details
Abstract / Simplified / High-Level View
9
Fetch Instruction Functional Unit
Fetch the Instruction: mem[PC] Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- “some other address” PC Adder Sum 4 Instruction address memory 32
10
Fetch Instruction Functional Unit
Fetch the Instruction: mem[PC] Update the program counter: Sequential Code: PC <- PC + 4 Branch and Jump: PC <- “some other address” PC Adder Sum 4 Instruction address memory 32
11
Arithmetic Instructions
addU rd, rs, rt R[rd] <- R[rs] + R[rt] ALUoperation Control logic after decoding the instruction Instructs the ALU as to the proper operation for the instruction RegWrite Asserted to store result in a register
12
Arithmetic Instructions
op rs rt rd shamt funct 6 11 16 21 26 31 6 bits 5 bits Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A B ALU Result
13
Or Immediate ori rt, rs, imm16 R[rt] <- R[rs] || ZeroExt[imm16]
Destination register can be either rt or rd Select the correct instruction field for destination register address 11 op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits rd? immediate 16 15 31 16 bits
![Or Immediate ori rt, rs, imm16 R[rt] <- R[rs] || ZeroExt[imm16]](http://slideplayer.com/slide/17181731/99/images/13/Or+Immediate+ori+rt%2C+rs%2C+imm16+R%5Brt%5D+%3C-+R%5Brs%5D+%7C%7C+ZeroExt%5Bimm16%5D.jpg "Destination register can be either rt or rd. Select the correct instruction field for destination register address. 11. op. rs. rt. immediate bits. 16 bits. 5 bits. rd immediate bits")
14
Or Immediate How does the datapath for an R-type instruction change when Add a register to an immediate value R[rt] <- R[rs] || ZeroExt[imm16] A input to the ALU Read Data 1 from the register file Incorporate zero extension unit Add zero extended 16-bit immediate operand B input of ALU Read Data 2 Zero extended 16-bit immediate operand
15
Or Immediate I-type instruction datapath Added ALUsrc control signal
Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero extend 16 Imm B
16
R- and I-type Instructions
R-type and some I-type instructions datapath Added RegDst control signal Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result RegDst MUX ALUsrc zero extend 16 Imm B
17
Load Word Instruction lw rt, rs, imm16
R[rt] <- Mem[R[rs] + SignExt[imm16]] Compute effective address of the word to load Contents of rs added to a sign extended 16-bit immediate value Write the word to register rt 11 op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits rd
18
Load Word Instruction Same hardware for performing arithmetic and logical operations on an immediate operand Added a more general bit extender Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero sign extend 16 Imm B
19
Load Word Instruction Read a word from memory given the address on the Result line Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm Data Out Data In Write Enable Addr Data Memory MemWrite B
20
Load Word Instruction Word read from memory must be saved in register rt ALU result is connected to the Write Data line of the register file Read register number 1 RegWrite Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm Data Out Data In Write Enable Addr Data Memory MemWrite B
21
Load Word Instruction Add a multiplexor to select one of two outputs
The ALU and the Data Memory Read register number 1 RegWr Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm Data Out Data In Write Enable Addr Data Memory MemWr MemToReg B
22
Store Word Instruction
sw rt, rs, imm16 Mem[ R[rs] + SignExt[imm16] ]<- R[rt] Compute effective address of the word to store Contents of rs added to a sign extended 16-bit immediate value Read the word in register rt op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits
23
Store Word Instruction
Same hardware for performing Arithmetic and logical operations on an immediate operand Load word effective address computation Read register number 1 RegWr Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm B
24
Store Word Instruction
Read a word from register rt and store at the given address on the Result line Connect read register 2 line of the register file to the Data In line of the data memory Read register number 1 RegWr Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm Data Out Data In Write Enable Addr Data Memory MemWr MemToReg B
25
The Branch Instruction
op rs rt immediate 16 21 26 31 6 bits 16 bits 5 bits beq rs, rt, imm16 Equal <- R[rs] == R[rt] Calculate the branch condition if (COND eq 0) Calculate address of next instruction PC <- PC (Shift left 2 bits(SignExt(imm16) x 4 )) else PC <- PC + 4 Next instruction logic from before
26
The Branch Instruction
beq rs, rt, imm16 Equal <- R[rs] == R[rt] Calculate the branch condition PC Instruction Address Instruction Instruction Memory Next Address Logic
27
The Branch Instruction
beq rs, rt, imm16 Two inputs for the PC PC = PC + 4 and PC = PC ( SignExt(imm16) x 4 ) PC Adder Sum Instruction Address 4 Instruction Instruction Memory PCSrc MUX 32 zero-sign extend 16 Imm Shift left 2 New control signal
28
All together
29
4 MUX Instruction Memory ALU MUX Data Memory Shift left 2
PC Adder Sum 4 Instruction Address Instruction Instruction Memory PCSrc MUX 32 zero-sign extend 16 Imm Shift left 2 Read register number 1 RegWr Clk number 2 Write register data Read data 1 data 2 5 32 Rs Rt Rd ALUoperation A ALU Result ALUsrc MUX zero-sign extend 16 Imm Data Out Data In Write Enable Addr Data Memory MemWr MemToReg B
30
Data Path 4 MUX Instruction Memory Shift left 2 zero-sign extend PCSrc
Adder Sum 4 Instruction Address Instruction Instruction Memory PCSrc MUX 32 zero-sign extend 16 Imm Shift left 2
Similar presentations
![Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]](/26/8775260/big_thumb.jpg "Computer Architecture and Design – ECEN 350 Part 6 [Some slides adapted from A. Sprintson, M. Irwin, D. Paterson and others]>")