1. COSC 3430 L08 Basic MIPS Architecture.1 COSC 3430 Computer Architecture Lecture 08 Processors Single cycle Datapath PH 3: Sections 5.1-5.4

2. COSC 3430 L08 Basic MIPS Architecture.2 Introduction  CPU performance factors l Instruction count -Determined by ISA and compiler l CPI and Cycle time -Determined by CPU hardware  We will examine two MIPS implementations in this chapter l A simplified single cycle version l A multicycle implementation l In the next chapter we will see a more realistic pipelined version

3. COSC 3430 L08 Basic MIPS Architecture.3 Review: THE Performance Equation  The basic performance equation is CPU time = Instruction_count x CPI x clock_cycle Instruction_count x CPI clock_rate CPU time = ----------------------------------------------- or  These equations separate the three key factors that affect performance l Can measure the CPU execution time by running the program l The clock rate is usually given in the documentation l Can measure instruction count by using profilers/simulators without knowing all of the implementation details l CPI varies by instruction type and ISA implementation for which we must know the implementation details

4. COSC 3430 L08 Basic MIPS Architecture.4  Our implementation of the MIPS is simplified memory-reference instructions: lw, sw arithmetic-logical instructions: add, sub, and, or, slt control flow instructions: beq, j  Generic implementation l use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) l decode the instruction (and read registers) l execute the instruction  All instructions (except j ) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 DecodeExec

5. COSC 3430 L08 Basic MIPS Architecture.5 Instruction Execution  PC  instruction memory, fetch instruction  Register numbers  register file, read registers  Depending on instruction class l Use ALU to calculate -Arithmetic result -Memory address for load/store -Branch target address l Access data memory for load/store l PC  target address or PC + 4

6. COSC 3430 L08 Basic MIPS Architecture.6 Clocking Methodologies  The clocking methodology defines when signals can be read and when they are written l An edge-triggered methodology  Typical execution l read contents of state elements l send values through combinational logic l write results to one or more state elements State element 1 State element 2 Combinational logic clock one clock cycle  Assumes state elements are written on every clock cycle; if not, need explicit write control signal l write occurs only when both the write control is asserted and the clock edge occurs

7. COSC 3430 L08 Basic MIPS Architecture.7 Clocking Methodology  Combinational logic transforms data during clock cycles l Between clock edges l Input from state elements, output to state element l Longest delay determines clock period

8. COSC 3430 L08 Basic MIPS Architecture.8 CPU Overview (Simplified example circuit)

9. COSC 3430 L08 Basic MIPS Architecture.9 Multiplexers  Can’t just join wires together l Use multiplexers

10. COSC 3430 L08 Basic MIPS Architecture.10 Building a Datapath  Datapath l Elements that process data and addresses in the CPU -Registers, ALUs, mux’s, memories, …  We will build a MIPS datapath incrementally l Refining the overview design

11. COSC 3430 L08 Basic MIPS Architecture.11 Fetching Instructions  Fetching instructions involves l reading the instruction from the Instruction Memory l updating the PC to hold the address of the next instruction Read Address Instruction Memory Add PC 4 l PC is updated every cycle, so it does not need an explicit write control signal l Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

12. COSC 3430 L08 Basic MIPS Architecture.12 Decoding Instructions  Decoding instructions involves l sending the fetched instruction’s opcode and function field bits to the control unit Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit l reading two values from the Register File -Register File addresses are contained in the instruction

13. COSC 3430 L08 Basic MIPS Architecture.13 Executing R Format Operations  R format operations ( add, sub, slt, and, or ) l perform the (op and funct) operation on values in rs and rt l store the result back into the Register File (into location rd) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: 3125201550 oprsrtrdfunctshamt 10 The Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File

14. COSC 3430 L08 Basic MIPS Architecture.14 Executing Load and Store Operations  Load and store operations involves l compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction l store value (read from the Register File during decode) written to the Data Memory l load value, read from the Data Memory, written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

15. COSC 3430 L08 Basic MIPS Architecture.15 Executing Branch Operations  Branch operations involves compare the operands read from the Register File during decode for equality ( zero ALU output) l compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

16. COSC 3430 L08 Basic MIPS Architecture.16 Executing Jump Operations  Jump operation involves l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address 26 4 28

17. COSC 3430 L08 Basic MIPS Architecture.17 Creating a Single Datapath from the Parts  Assemble the datapath segments and add control lines and multiplexors as needed  Single cycle design – fetch, decode and execute each instructions in one clock cycle l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) l multiplexors needed at the input of shared elements with control lines to do the selection l write signals to control writing to the Register File and Data Memory  Cycle time is determined by length of the longest path

18. COSC 3430 L08 Basic MIPS Architecture.18 Fetch, R-type, and Memory Access Portions MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

19. COSC 3430 L08 Basic MIPS Architecture.19 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs) I-Type: oprsrt address offset 312520150 R-type: 3125201550 oprsrtrdfunctshamt 10  Observations l op field always in bits 31-26 l addr of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0 J-type: 31250 optarget address

20. COSC 3430 L08 Basic MIPS Architecture.20 Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

21. COSC 3430 L08 Basic MIPS Architecture.21 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

22. COSC 3430 L08 Basic MIPS Architecture.22 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

23. COSC 3430 L08 Basic MIPS Architecture.23 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

24. COSC 3430 L08 Basic MIPS Architecture.24 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

25. COSC 3430 L08 Basic MIPS Architecture.25 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

26. COSC 3430 L08 Basic MIPS Architecture.26 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 0 0 0 0 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left 2 0 1 Jump 32 Instr[25-0] 26 PC+4[31-28] 28

27. COSC 3430 L08 Basic MIPS Architecture.27 An important point about the datapath  In this data path we see several shift left 2 functions and sign extend functions. They are crucial functions if the circuit is to work properly.  On the next chart is a circuit that will take the contents of a 4 bit register and shift it into a 4 bit register with its bits shifted 0, 1, 2, or 3 bits by using 4, 4 to 1 mulitplexers. This idea could be extended to a 32 bit multiplexer that would allow shifts of 0 to 31 bits (shamt is 5 bits)  The sign extend is relatively easy. All that needs to be done is feed the bits 0-15 into the least significant bits of a register and allow the 15 th bit to fill the remaining bits 16-31.

28. COSC 3430 L08 Basic MIPS Architecture.28 A left shifter circuit, 0 to 3 bits x 0, x 1, x 2, x 3 are inputs from a 4 bit register z 0, z 1, z 2, z 3 are outputs to a 4 bit register. s1 and s0 are the selector inputs for the number of bits to shift, 00, 01, 10, 11. The input 5 is 0.

29. COSC 3430 L08 Basic MIPS Architecture.29 Problem  1. Discuss how the general shifter, (0 to 31 bits) could be implemented.  2. Since in our simple example we only need to shift left 2 bits, show how this can be done.

30. COSC 3430 L08 Basic MIPS Architecture.30 Next Lecture and Reminders  Next lecture l MIPS processor: single cycle control and multicycle -Reading assignment – PH, Chapter 5.4-5.5