2 Components of a Computer ProcessorControlDatapathMemoryDevicesInputOutput
3 Code Stored in Memory Memory Processor Devices Control Input Datapath ControlInputDatapathOutput2. These data are kept in the computer’s memory until ...Note that memory holds both INSTRUCTIONS and DATA and you can’t tell the difference. They are both just 32 bit strings of zeros and ones.
4 Processor Fetches an Instruction Processor fetches an instruction from memoryMemoryProcessorDevicesControlInputDatapathOutput3. The processor request and process them.
5 Control Decodes the Instruction Control decodes the instruction to determine what to executeProcessorDevicesControlMemoryInputDatapathOutput3. The processor control decodes the instruction in order to figure out what to tell the datapath to do
6 Datapath Executes the Instruction Datapath executes the instruction as directed by controlProcessorDevicesControlMemoryInputDatapathcontents Reg #4 ADD contents Reg #2results put in Reg #2Output4. The operation of the datapath is controlled by the processor’s controller.
7 What Happens Next? Memory Processor Devices Control Input Datapath ControlInputDatapathOutputFor lecture3. What happens next (next instruction is fetched/how to tell where that instruction is located in memory/…)FetchExecDecode
8 Output Data Stored in Memory At program completion the data to be output resides in memoryMemoryProcessorDevicesControlInputDatapathOutput5. The data to be output are kept in the computer’s memory until ...
10 Design of Processor Analyze the instruction set architecture Select the datapath elements each instruction needsAssemble the datapathdetermine the controls requiredAssemble the control logic
11 A Basic MIPS Implementation will implement the following subset of MIPS core instructionslw, swadd, sub, and, or, sltbeq, j
12 Steps in executing add instruction add $t0, $t1, $t2Send PC to memory that contains the code and fetch instructionPC = PC+4Read $t1 and $t2 from register filePerform $t1 + $t2Store result in $t0
13 Steps in executing lw instruction lw $t0, offset($t1)Send PC to memory that contains the code and fetch instructionPC = PC+4Read $t1 from register filePerform $t1 + sign-extend(offset)Read value at Mem[$t1 + sign-extend(offset)]Store result in $t0
14 Steps in executing beq instruction beq $t0, $t1, LabelSend PC to memory that contains the code and fetch instructionPC = PC+4Read $t0 and $t1 from register filePerform $t0 - $t1If result = 0, set PC=Label
15 Steps in implementing these instructions Common stepsSend PC to memory that contains the code and fetch the instructionSet PC = PC+4Read one or two registersSteps dependent on instruction classUse ALUArithmetic/logical instr for operation executionlw/sw for address calculationbeq for comparisonUpdate memory or registerslw/sw read or write to memoryArithmetic/logical instr write to registerbeq updates PC
16 Components needed for Fetching and Incrementing PC
19 Register FileConsists of a set of 32 registers that can be read and writtenRegisters built from D flip-flopshas two read ports and one write portRegister number are 5 bit longTo write, you need three inputs:a register number, the data to write, and a clock (not shown explicitly) that controls the writing into the registerThe register content will change on rising clock edge555Write signal must be asserted to write the data to register on rising edgeRegister numbers are 5 bitsWhat happens if the same register is read and written during a clock cycle? Because the write of the register file occurs on the clock edge, the register will be valid during the time it is read, The value returned will be the value written in an earlier clock cycle
20 Portion of datapath for R-format instruction 4rsrtrd31-2625-2120-1615-1110-65-0opcodersrtrdshamtfunctR-format
21 Components needed for load and store instructions lw $t0, offset($t1): $t0=Mem[$t1 + se(offset)]sw $t0, offset($t1): Mem[$t1 + se(offset)]=$t0
22 Memory Unit MemRead to be asserted to read MemWrite to be asserted to writeBoth MemRead and MemWrite not to be asserted in same clock cycleMemory is edge triggered for writesAddressReadDataWrite DataMemWrite
27 Creating a single Datapath Simplest Design: Single Cycle ImplementationAny instruction takes one clock cycle to executeThis means no datapath elements can be used more than once per instructionBut datapath elements can be shared by different instruction flows
29 Composite Datapath for R-format and load/store instructions
30 Composite Datapath for R-format and load/store instructions 4+PCInstruction Memory
31 Composite datapath for R-format, load/store, and branch instructions
32 Datapath for for R-format, load/store, and branch instructions ALU Operation4
33 R-format 1 0000(and) 0001(or) 0010(add) 0110(sub) lw 0010 (add) sw X InstructionRegDstRegWriteALUSrcMemReadMemWriteMemToRegPCSrcALU operationR-format10000(and)0001(or)0010(add)0110(sub)lw0010 (add)swXbeqx1 or 00110 (sub)
34 Control We next add the control unit that generates write signal for each state elementcontrol signals for each multiplexerALU control signalInput to control unit: instruction opcode and function code
35 Control Unit Divided into two parts Main Control Unit ALU Control Unit Input: 6-bit opcodeOutput: all control signals for Muxes, RegWrite, MemRead, MemWrite and a 2-bit ALUOp signalALU Control UnitInput: 2-bit ALUOp signal generated from Main Control Unit and 6-bit instruction function codeOutput: 4-bit ALU control signal
39 ALU Control UnitMust describe hardware to compute 4-bit ALU control input given2-bit ALUOp signal from Main Control Unitfunction code for arithmeticDescribe it using a truth table (can turn into gates):