Presentation on theme: "Levels in Processor Design"— Presentation transcript:
1 Levels in Processor Design Circuit designKeywords: transistors, wires etc.Results in gates, flip-flops etc.Logical designPutting gates (AND, NAND, …) and flip-flops together to build basic blocks such as registers, ALU’s etc (cf. CSE 370)Register transferDescribes execution of instructions by showing data flow between the basic blocksProcessor description (the ISA)System descriptionIncludes memory hierarchy, I/O, multiprocessing etcCSE378 Single cycleimplementation.
2 Register transfer level Two types of components (cf. CSE 370)Combinational : the output is a function of the input (e.g., adder)Sequential: state is remembered (e.g., register)CSE378 Single cycleimplementation.
3 Synchronous design Use of a periodic clock edge-triggered clocking determines when signals can be read and when the output of circuits is stableValues in storage elements can be updated only at clock edgesClock tells when events can occur, e.g., when signals sent by control unit are obeyed in the ALUNote: the same storage element can be read/written in the same cycleStor. Elem 1Stor. Elem 2Comb.logicClock cycleCSE378 Single cycleimplementation.
4 Processor design: data path and control unit CPUCombinationalMemory hierarchycontrolALUPCRegistersstateSequentialMemory busData pathCSE378 Single cycleimplementation.
5 Processor design Data path Control unit Memory hierarchy How does data flow between various basic blocksWhat operations can be performed when data flowsWhat can be done in one clock cycleControl unitSends signals to data path elementsTells what data to move, where to move it, what operations are to be performedMemory hierarchyHolds program and dataCSE378 Single cycleimplementation.
6 Data path basic building blocks. Storage elements Basic building block (at the RT level) is a registerIn our mini-MIPS implementation registers will be 32-bitsA register can be read or writtenInput busRegisterWrite enable signalOutput busCSE378 Single cycleimplementation.
7 Register fileArray of registers (32 for the integer registers in MIPS)ISA tells us that we should be able to:read 2 registers, write one register in a given instruction (at this point we want one instruction per cycle)Register file needs to know which registers to read/writeRead register number bus 0Write register numberRead register number bus 1Write enableRead data output bus 0Write data input busRegister fileRead data output bus 1CSE378 Single cycleimplementation.
8 Memory Conceptually, like register file but much larger Can only read one location or write to one location per cycleRead memory addressWrite memory addressRead control signalWrite enableMemoryRead data busWrite data busCSE378 Single cycleimplementation.
9 Combinational elements Multiplexor (MUX): selects the value of one of its inputs to be routed to the outputInput bussesMuxSelect control signalDemultiplexor (deMUX or SEL): routes its input to one of its outputsOutput busOutput bussesSelSelect control signalInput busCSE378 Single cycleimplementation.
10 Arithmetic and Logic Unit (ALU - combinational) Computes (arithmetic or logical operation) output from its two inputsZero result bitInput bus 0ALUOutput busInput bus 1ALU control (opcode/function)CSE378 Single cycleimplementation.
11 Putting basic blocks together (skeleton of data path for arith/logical operations) Zero result bitRead register number bus 0Write register numberRead register number bus 1Write enableRead data 0ALURegister fileRead data 1ALU control (opcode/function)Write data input busCSE378 Single cycleimplementation.
12 Introducing instruction fetch Zero result bitRead Reg #0Read Reg #1Write Reg #Read data 0ALUReg. FileRead data 1ALU control (opcode/function)Write dataInstruction addressInstr. memoryPCCSE378 Single cycleimplementation.
13 PC has to be incremented (assume no branch) 4AdderInstruction addressInstructionInstr. memoryPCCSE378 Single cycleimplementation.
14 Load-Store instructions Read enableInstructionRead data 0Read Reg #0Read Reg #1Write Reg #ALUData memoryR/W addressReg. File32-bit“store” dataSignextend16-bit offsetWrite enableData from “load”CSE378 Single cycleimplementation.
15 Data path for straight code (reg-reg,imm,load/store) Read enableInstructionRead data 0Read Reg #0Read Reg #1Write Reg #ALURead data 1Data memoryR/W addressReg. File32-bitSign.ext“store” data16-bit offsetWrite enableData for result registerMuxCSE378 Single cycleimplementation.
16 Branch data path ALU 4 Adder Inst. memory PC sll 2 32-bit Instruction Sign.extCSE378 Single cycleimplementation.
17 Control UnitControl unit sends control signals to data path and memory dependingon the opcode (and function field)results in the ALU (for example for Zero test)These signals controlmuxes; read/write enable for registers and memory etc.Some “control” comes directly from instructionregister namesSome actions are performed at every instruction so no need for control (in this single cycle implementation)incrementing PC by 4; reading instr. memory for fetching next inst.CSE378 Single cycleimplementation.
18 Building the control unit Decompose the problem intoData path control (register transfers)ALU controlSetting of control lines by control unit totally specified in the ISAfor ALU by opcode + function bits if R-R formatfor register names by instruction (including opcode)for reading/writing memory and writing register by opcodemuxes by opcodePC by opcode + result of ALUCSE378 Single cycleimplementation.
19 Example Limit ourselves to: ALU control R-R instructions: add, sub, and, or, slt –OPcode = 0 but different function bitsLoad-store: lw, swBranch: beqALU controlNeed to add for: add, lw, swNeed to sub for: sub, beqNeed to and for :andNeed to or for :orNeed to set less than for : sltCSE378 Single cycleimplementation.
20 ALU Control ALU control: combination of opcode and function bits Decoding of opcodes yields 3 possibilities hence 2 bitsAluOp1 and ALUOp2ALU control:Input 2 ALUop bits and 6 function bitsOutput one of 5 possible ALU functionsOf course lots of don’t care for this *very* limited implementationCSE378 Single cycleimplementation.
21 Implementation of Overall Control Unit Input: opcode (and function bits for R-R instructions)Output: setting of control linesCan be done by logic equationsIf not too many, like in RISC machinesUse of PAL’s (cf. CSE 370).In RISC machines the control is “hardwired”If too large (too many states etc.)Use of microprogramming (a microprogram is a hardwired program that interprets the ISA)Or use a combination of both techniques (Pentium)CSE378 Single cycleimplementation.
22 Where are control signals needed (cf. Figure 5.15) Register fileRegWrite (Register write signal for R-type, Load)RegDst (Register destination signal: rd for R-type, rt for Load)ALUALUSrc (What kind of second operand: register or immediate)ALUop (What kind of function: ALU control for R-type)Data memoryMemRead (Load) or MemWrite (Store)MemtoReg (Result register written from ALU or memory)Branch controlPCSrc (PC modification if branch is taken)CSE378 Single cycleimplementation.
23 How are the control signals asserted Decoding of the opcode by control unit yieldsControl of the 3 muxes (RegDst, ALUSrc,MemtoReg): 3 control linesSignals for RegWrite, Memread,Memwrite: 3 control linesSignals to activate ALU control (e.g., restrict ourselves to 2)Signal for branch (1 control line)decoding of opcode ANDed with ALU zero resultInput Opcode: 6 bitsOutput 9 control lines (see Figure 5.17)CSE378 Single cycleimplementation.