1. CS/COE0447 Computer Organization & Assembly Language
Chapter 5
Part 1

2. Memory reference instructions Arithmetic-logical instructions
We will study the datapath and control using only these instructions [similar ideas apply to others]
Memory reference instructions
lw (load word) and sw (store word)
Arithmetic-logical instructions
add, sub, and, or, and slt
Control-transfer instructions
beq (branch if equal)
j (unconditional jump)

3. An Abstract Implementation (fig 5.1)
Combinational logic
ALU, adder
Sequential logic
Register file, instruction memory, data memory

4. Building Blocks (figs 5.7-5.8)

5. from which instruction
Instruction Fetch
Instruction width
is 4 bytes!
PC keeps the current
memory address
from which instruction
is fetched
Instruction memory
here is read-only!

6. Instruction Execution
lw (load word)
Fetch instruction lw $t0,-12($t1)
Read a base register $t1
Sign-extend the immediate offset fff4  fffffff4
Add two values to get address X = fffffff4 + $t1
Access data memory with the address M[X]
Store the memory data to the destination register $t0

7. Memory + R-Instructions (fig 5.10)
E.G: lw $t0,8($t1)
Load data
from memory
Imm. offset
for address
To be in
a register!

8. Instruction Execution, cont’d
add
Fetch instruction
Read two source registers
Add two values
Store the result to the destination register

9. Memory + R-Instructions (fig 5.10)
E.G: add $t2,$t1,$t0

10. Instruction Execution, cont’dj
Fetch instruction
Take the 26-bit immediate field
Shift left by 2 (to make 28-bit immediate)
Get 4 bits from the current PC and attach to the left of the immediate
Assign the value to PC

11. Branch Datapath (fig. 5.9)

12. Memory + R-Instructions (fig 5.10)
E.G: sw $t0,8($t1)

13. Memory + R-Instructions (fig 5.10)
E.G: add $t0,$t1,$t2; MUX selections are reversed

14. Datapath so far (fig 5.11)
j not considered
so far!

15. Instruction Format

16. More Elaborated Design (fig 5.15)
Write register #
selection
ALU control bits
from I[5:0]

17. A First Look at Control (fig 5.17)

18. Control Signals Overview
RegDst: which instr. field to use for dst. register specifier?
instruction[20:16] vs. instruction[15:11]
ALUSrc: which one to use for ALU src 2?
immediate vs. register read port 2
MemtoReg: is it memory load?
RegWrite: update register?
MemRead: read memory?
MemWrite: write to memory?
Branch: is it a branch?
ALUop: what type of ALU operation?

19. Generic Control Sequence
For each fetched instruction
(decoding)
Select two registers to read from register file
Select the 2nd ALU input
Select ALU operation
Select if data memory is to be accessed
Select if register file is updated
Select what to assign to PC