1. The Processor Lecture 3.1: Introduction & Logic Design Conventions
Be aware that this first part of new chapter 4 is review for this class, so doesn’t go into detail. If your students are learning computer organization for the first time, this set of slides needs to be expanded greatly.

2. Learning Objectives
Describe the steps in the generic implementation of the processor
Explain what ALU (arithmetic logic unit) does for each of 9 instructions
Define the basic behavior of registers
Understand the edge-triggered methodology

3. Coverage Chapter 4.1: Introduction
Chapter 4.2: Logic Design Conventions

4. Introduction
Chapter 4.1

5. Review: MIPS (RISC) Design Principles
Simplicity favors regularity
fixed size instructions
small number of instruction formats
opcode always the first 6 bits
Smaller is faster
limited instruction set
limited number of registers in register file
limited number of addressing modes
Make the common case fast
arithmetic operands from the register file (load-store machine)
allow instructions to contain immediate operands
Good design demands good compromises
three instruction formats

6. The Processor: Datapath & Control
Our implementation of the MIPS is simplified
memory-reference instructions: lw, sw
arithmetic-logical instructions: add, sub, and, or, slt
control flow instructions: beq, j
Generic implementation
use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC)
decode the instruction (and read registers)
execute the instruction
All instructions (except j) use the ALU after reading the registers
How? memory-reference? arithmetic? control flow?
Fetch
PC = PC+4
Decode
Exec
memory reference use ALU to compute addresses
arithmetic use the ALU to do the require arithmetic
control use the ALU to compute branch conditions.

7. Logic Design Conventions
Chapter 4.2

8. Logic Design Basics Information encoded in binary
Low voltage = 0, High voltage = 1
One wire per bit
Multi-bit data encoded on multi-wire buses
Combinational components
Operate on input
Output is a function of input
State (sequential) components
Store information

9. Combinational Components
AND-gate
Y = A & B A B Y A B Y +
Adder
Y = A + B I1 I0 Y
M u x S
Multiplexer
Y = S ? I1 : I0 A B Y
ALU F
Arithmetic/Logic Unit
Y = F(A,B)

10. Sequential Components
Register: stores data in a circuit
Uses a clock signal to determine when to update the stored value
Edge-triggered: update when the clock signal changes the value
Rising edge (positive edge) : 0→1
Falling edge (negative edge) : 1→0
D flip-flop is one option to implement register
Clk D Q
Use the thermometer and thermostat example.
There is a thermometer in the hallway. At the beginning of every clock, I open the door, read the thermometer and set the thermostat in the house based on the reading. D
Clk Q

11. Sequential Components
Register with write control
Only updates on clock edge when write control input (e.g., Write Enable) is asserted WE D Q
Clk D
Clk Q WE

12. Clocking Methodologies
The clocking methodology defines when data in a state element are valid and stable relative to the clock
State elements – an element such as a register
Edge-triggered – all state changes occur on a clock edge
Typical execution
read contents of state elements → send values through combinational logic → write results to one or more state elements
State
element 1
State
element 2
Combinational
logic
State elements (a memory element) – instruction memory, data memory, registers
With edge-triggered state elements, there is no worry about feedback within a single clock cycle (it’s a single-sided clock constraint (just have to worry about making sure the clock is long enough, don’t have to worry about it being too short))
clock
one clock cycle
Assumes state elements are written on every clock cycle; if not, need explicit write control signal
write occurs only when both the write control is asserted and the clock edge occurs