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MIPS processor continued

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1 MIPS processor continued

2 Jump Instruction Jump instruction seems easy to implement
We just need to replace the lower 28 bits of the PC with the lower 26 bits of the instruction shifted by 2 bits The shift is achieved by simply concatenating 00 to the jump offset 11/15/2007 5:02:11 PM week-13-3.ppt

3 Implementing Jumps The one we have supports arithmetic/logic instructions, branch instructions, load and store instructions We need also to support the jump instruction What are the changes we need to make? 1 31 opcode Address 26 25

4 Add j?

5 Supporting Jump Instruction

6 In Class Exercise – Supporting Jump Register
11/25/ :54:43 PM week-14-1.ppt

7 Performance Assume that How fast is
Memory access: 200ps ALU and adders: 100 ps Register file read: 50ps Register file write: 10ps (the clk-to-q delay) PC update: 10ps (the clk-to-q delay) The setup time of DFFs: 10ps Other parts do not have delay How fast is An R-type instruction? A lw instruction? A sw instruction? A beq instruction? Need to find the critical path – the longest path

8 R-type So, the clock needs to be at least 10+200+50+100+10 = 370ps
PC ready instruction ready register ready ALU ready register written So, the clock needs to be at least = 370ps Will there be a problem if the next instruction is also an R-type instruction, considering that the register is written and stable only after the next rising edge of the clock? Figure not to the exact scale Note that once the instruction is stable, all control signals are stable, so the D signals to the D flip flops are stable. Ultimately what we change is the D signal – either the old Q or some new stuff. They will not change until the next rising edge of the clock, so the D will be stable till the next rising edge of the clock – all that we cares.

9 lw So, the clock needs to be at least 10+200+50+100+200+10 = 570ps
PC ready instruction ready register ready ALU ready Data mem ready register written So, the clock needs to be at least = 570ps Figure not to the exact scale

10 beq So, it is 10+200+50+100+10 = 370ps Figure not to the exact scale
PC ready instruction ready register ready ALU ready Adder 1 ready Adder 2 ready So, it is = 370ps Figure not to the exact scale

11 Clock cycle So, how long should the clock cycle be? Is it efficient?

12 Control Signals Control signals include ALUCtrl and the signals to control the 2-1 selectors They are generated according to the current instruction, using the opcode [31-27] and the funct [5-0] field in the instruction.

13 Datapath for Memory, R-type and Branch Instructions, plus the control signals

14 The Effect of Control Signals
Signal name Effect when deasserted Effect when asserted RegDst The register destination number for the Write register comes the rt field (20:16) The register destination number for the Write register comes the rd field (15:11) RegWrite None. The register on the Write register input is written with the value on the Write data input. ALUSrc The second ALU operand comes from the second register file output The second ALU operand is the sign-extended, lower 16 bits of the instruction PCSrc The PC is replaced by the output of the adder that computes the value of PC + 4 The PC is replaced by the output of the adder that computes the branch target MemRead Data memory contents designated by the address input are out on the Read data output. MemWrite Data memory contents designated by the address input are replaced by the value on the Write data input. MemtoReg The value fed to the register Write data input comes from the ALU The value fed to the register Write data input comes from the data memory

15 Table for Control Line Setting
Note: Branch is anded with ALU zero output to produce PCSrc Instruction RegDst ALUSrc Memto- Reg Write Mem Read Branch ALUOp1 ALUOp0 R-format Lw Sw beq

16 Table for Control Line Setting
Instruction RegDst ALUSrc Memto- Reg Write Mem Read Branch ALUOp1 ALUOp0 R-format 1 lw sw X beq

17 Truth Table for Control Function

18 Implementation Using PLA
R lw sw beq The way to read this -- There are only 4 possible combination of inputs

19 MIPS ALU unit

20 ALU Control Use Opcode to get ALUOp, then combine ALUOp with Funct
Two levels of decoding, more efficient Assume ALUOp has been determined as such for each instruction 11/15/2007 5:02:13 PM week-13-3.ppt

21 One Implementation ALU control bit 3 is always 0 for this set of instructions Can verify that the output is correct for lw, sw, beq For R-type, op2=F1, op1= ~F2, op0 = F3 | F0

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