1. Multi-Cycle Datapath and Control
Lecture 6
Multi-Cycle Datapath and Control

2. Single-cycle implementation
As we’ve seen, single-cycle implementation, although easy to implement, could potentially be very inefficient In single-cycle, we define a clock cycle to be the length of time needed to execute a single instruction. So, our lower bound on the clock period is the length of the most- time consuming instruction In our previous example, our jump instruction needs only 4ns but our clock period must be 13ns to accommodate the load word instruction!

3. Multi-cycle implementation
We can get around some of the disadvantages by introducing a little more complexity to our datapath.
Instead of viewing the instruction as one big task that needs to be performed, in multi-cycle the instructions are broken up into smaller fundamental steps As a result, we can shorten the clock period and perform the instructions incrementally across multiple cycles.
What are these fundamental steps? Well, let’s take a look at what our instructions actually need to do…

4. R-format steps
An instruction is fetched from instruction memory and the PC is incremented.
Read two source register values from the register file.
Perform the ALU operation on the register data operands.
Write the result of the ALU operation to the register file.

5. Load steps
An instruction is fetched from instruction memory and the PC is incremented.
Read a source register value from the register file and sign-extend the 16 least significant bits of the instruction.
Perform the ALU operation that computes the sum of the value in the register and the sign-extended immediate value from the instruction.
Access data memory at the address given by the result from the ALU.
Write the result of the memory value to the register file.

6. Store steps
An instruction is fetched from instruction memory and the PC is incremented.
Read two source register values from the register file and sign-extend the 16 least significant bits of the instruction.
Perform the ALU operation that computes the sum of the value in the register and the sign-extended immediate value from the instruction.
Update data memory at the address given by the result from the ALU.

7. Branch equal steps
An instruction is fetched from instruction memory and the PC is incremented.
Read two source register values from the register file and sign-extend the 16 least significant bits of the instruction and then left shifts it by two.
The ALU performs a subtract on the data values read from the register file. The value of PC+4 is added with the sign-extended left-shifted by two immediate value from the instruction, which results in the branch target address.
The Zero result from the ALU is used to decide which adder result should be used to update the PC.

8. Jump steps
An instruction is fetched from instruction memory and the PC is incremented.
Concatenate the four most significant bits of PC+4, the 26 least significant bits of the instruction, and two zero bits. Assign the result to the PC.

9. General steps
So, generally, we can say we need to perform the following steps:
Instruction Fetch Step.
Instruction Decode and Register Fetch Step.
Execution, Memory Address Computation, Branch Completion Step, or Jump Completion Step.
Memory Access or R-Type Instruction Completion Step.
Memory Read Completion Step.

10. Multi-cycle datapath
Here is a general overview of our new multi-cycle datapath.
We now have a single memory element that interacts with both instructions and data.
Single ALU unit, no dedicated adders.
Several temporary registers.

11. Multi-cycle datapath

12. Multi-cycle datapath
These are some old datapath elements that we are already used to. Note, however, that the Memory element is now pulling double-duty as both the Instruction Memory and Data Memory element.

13. Multi-cycle datapath

14. Multi-cycle datapath New Temporary Registers:
Instruction Register (IR) – holds the instruction after its been pulled from memory.
Memory Data Register (MDR) – temporarily holds data grabbed from memory until the next cycle.
A – temporarily holds the contents of read register 1 until the next cycle.
B – temporarily holds the contents of read register 2 until the next cycle.
ALUout – temporarily holds the contents of the ALU until the next cycle.
Note: every register is written on every cycle except for the instruction register.

15. Multi-cycle datapath

16. Multi-cycle datapath The IorD control signal.
Deasserted: The contents of PC is used as the Address for the memory unit.
Asserted: The contents of ALUout is used as the Address for the memory unit.

17. Multi-cycle datapath

18. Multi-cycle datapath The RegDst control signal.
Deasserted: The register file destination number for the Write register comes from the rt field.
Asserted: The register file destination number for the Write register comes from the rd field.

19. Multi-cycle datapath

20. Multi-cycle datapath The MemToReg control signal.
Deasserted: The value fed to the register file input comes from ALUout.
Asserted: The value fed to the register file input comes from MDR.

21. Multi-cycle datapath

22. Multi-cycle datapath
One of the changes we’ve made is that we’re using only a single ALU. We have no dedicated adders on the side. To implement this change, we need to add some multiplexors.
ALUSrcA multiplexor chooses between the contents of PC or the contents of temporary register A as the first operand.
ALUSrcB multiplexor chooses between the contents of temporary register B, the constant 4, the immediate field, or the left-shifted immediate field as the second operand.

23. Multi-cycle datapath and control

24. Multi-cycle datapath and control
1-Bit Signal Name
Effect When Deasserted
Effect When Asserted
RegDst
The register file destination number for the Write register comes from the rt field.
The register file destination number for the Write register comes from the rd field.
RegWrite
None
Write register is written with the value of the Write data input.
ALUSrcA
The first ALU operand is PC.
The first ALU operand is A register.
MemRead
Content of memory at the location specified by the Address input is put on the Memory data output.
MemWrite
Memory contents of the location specified by the
Address input is replaced by the value on the
Write data input.

25. Multi-cycle datapath and control
1-Bit Signal Name
Effect When Deasserted
Effect When Asserted
MemToReg
The value fed to the register file input is ALUout.
The value fed to the register file input comes from Memory data register.
IorD
The PC supplies the Address to the Memory element.
ALUOut is used to supply the address to the memory unit.
IRWrite
None
The output of the memory is written into the
Instruction Register (IR).
PCWrite
The PC is written; the source is controlled by
PC-Source.
PCWriteCond
The PC is written if the Zero output from the ALU is also active.

26. Multi-cycle datapath and control
2-bit Signal
Value
Effect
ALUOp 00
The ALU performs an add operation. 01
The ALU performs a subtract operation. 10
The funct field of the instruction determines the operation.
ALUSrcB
The second input to ALU comes from the B register.
The second input to ALU is 4.
The second input to the ALU is the sign-extended, lower 16 bits of the Instruction Register (IR). 11
The second input to the ALU is the sign-extended, lower 16 bits of the IR shifted left by 2 bits.
PCSource
Output of the ALU (PC+4) is sent to the PC for writing.
The contents of ALUOut (the branch target address) are sent to the PC for writing.
The jump target address (IR[25-0] shifted left 2 bits and concatenated with PC + 4[31-28]) is sent to the PC for writing.

27. Multi-cycle datapath and control
Ok, so we already observed that our instructions can be roughly broken up into the following steps:
Instruction Fetch Step.
Instruction Decode and Register Fetch Step.
Execution, Memory Address Computation, Branch Completion Step, or Jump Completion Step.
Memory Access or R-Type Instruction Completion Step.
Memory Read Completion Step.
Instructions take 3-5 of the steps to complete. The first two are performed identically in all instructions.

28. Instruction fetch step
IR = Memory[PC]; PC = PC + 4;
Operations:
Send contents of PC to the Memory element as the Address.
Read instruction from Memory.
Write instruction into IR for use in next cycle.
Increment PC by 4.
So Fetch!

29. Instruction Fetch step
Signal
Value
PCWrite
IorD
MemRead
MemWrite
IRWrite
PCSource
ALUOp
ALUSrcB
ALUSrcA
RegWrite

30. Instruction Fetch step
Signal
Value
PCWrite 1
IorD
MemRead
MemWrite
IRWrite
PCSource 00
ALUOp
ALUSrcB 01
ALUSrcA
RegWrite

31. Instruction decode + Reg Fetch step
A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2);
Operations:
Decode instruction.
Optimistically read registers.
Optimistically compute branch target.

32. Instruction decode + Reg Fetch step
Signal
Value
ALUOp
ALUSrcB
ALUSrcA

33. Instruction decode + Reg Fetch step
Signal
Value
ALUOp 00
ALUSrcB 11
ALUSrcA

34. Execution step Here is where our instructions diverge.
Memory Reference:
ALUOut = A + sign-extend(IR[15-0]);
Arithmetic-Logical Reference:
ALUOut = A op B;
Branch:
if (A == B) PC = ALUOut;
Jump
PC = PC[31-28] || (IR[25-0] << 2);

35. Execution: Memory Reference
Signal
Value
ALUOp 00
ALUSrcB 10
ALUSrcA 1

36. Execution: arithmetic/logical op
Signal
Value
ALUOp 10
ALUSrcB 00
ALUSrcA 1

37. Execution: branch Signal Value ALUOp 01 ALUSrcB 00 ALUSrcA 1 PCSource
PCWriteCond

38. Execution: jump
Signal
Value
PCSource 10
PCWrite 1

39. Memory Access/R-type completion step
Memory Reference:
Load: MDR = Memory[ALUOut];
Store: Memory[ALUOut] = B;
R-type Instruction:
Reg[IR[15-11]] = ALUOut;

40. Memory access: Load
Signal
Value
MemRead 1
IorD
IRWrite

41. Memory access: Store
Signal
Value
MemWrite 1
IorD

42. R-type completion
Signal
Value
MemtoReg
RegWrite 1
RegDst

43. Read completion step
Load operation:
Reg[IR[20-16]] = MDR;

44. Read completion
Signal
Value
RegWrite 1
MemtoReg
RegDst

45. Multi-cycle datapath and control
So, now we know what the steps are and what happens in each step for each kind of instruction in our mini-MIPS instruction set To make things clearer, let’s investigate how multi-cycle works for a particular instruction at a time.

46. R-format
R-format instructions require 4 cycles to complete. Let’s imagine that we’re executing an add instruction add $s0, $s1, $s2
which has the following fields:
opcode rs rt rd
shamt
funct
000000
10001
10010
10000
00000
100000

47. R-format: Cycle 1 Signal Value PCWrite 1 IorD MemRead MemWrite IRWrite
MemRead
MemWrite
IRWrite
PCSource 00
ALUOp
ALUSrcB 01
ALUSrcA
RegWrite

48. R-format: cycle 2 Signal Value ALUOp 00 ALUSrcB 11 ALUSrcA
Note that we compute the speculative branching target in this step even though we will not need it. We have nothing better to do while we decode the instruction so we might as well.

49. R-format: cycle 3
Signal
Value
ALUOp 10
ALUSrcB 00
ALUSrcA 1

50. R-Format: Cycle 4
Signal
Value
MemtoReg
RegWrite 1
RegDst

51. Branch
Branch instructions require 3 cycles to complete. Let’s imagine that we’re executing a beq instruction beq $s0, $s1, L1
which has the following fields:
opcode rs rt
immed
000100
10001
10010
XXXXXXXXXXXXXXXX

52. Branch: Cycle 1 Signal Value PCWrite 1 IorD MemRead MemWrite IRWrite
MemRead
MemWrite
IRWrite
PCSource 00
ALUOp
ALUSrcB 01
ALUSrcA
RegWrite

53. Branch: cycle 2
Signal
Value
ALUOp 00
ALUSrcB 11
ALUSrcA

54. Branch: Cycle 3 Signal Value ALUOp 01 ALUSrcB 00 ALUSrcA 1 PCSource
PCWriteCond