Ratioed Logic.

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Presentation transcript:

Ratioed Logic

Ratioed Logic

Active Loads

Load Lines of Ratioed Gates

Pseudo-NMOS

Pseudo-NMOS NAND Gate VDD GND

Improved Loads

Improved Loads (2)

Example

Pass-Transistor Logic

NMOS-only switch

Solution 1: Transmission Gate

Resistance of Transmission Gate

Pass-Transistor Based Multiplexer VDD GND In1 S S In2

Transmission Gate XOR

Delay in Transmission Gate Networks

Elmore Delay (Chapter 8)

Delay Optimization

Transmission Gate Full Adder

(2) NMOS Only Logic: Level Restoring Transistor

Level Restoring Transistor

Solution 3: Single Transistor Pass Gate with VT=0

Complimentary Pass Transistor Logic

4 Input NAND in CPL

Dynamic Logic

Example

Transient Response

Dynamic 4 Input NAND Gate VDD Out In1 In2 In3 In4 f GND

Reliability Problems — Charge Leakage

Charge Sharing (redistribution)

Charge Redistribution - Solutions

Clock Feedthrough

Clock Feedthrough and Charge Sharing

Cascading Dynamic Gates

Domino Logic

Domino Logic - Characteristics

np-CMOS

np CMOS Adder

Manchester Carry Chain Adder

CMOS Circuit Styles - Summary