1. Pass Transistor Logic

2. Agenda  Introduction  VLSI Design methodologies  Review of MOS Transistor Theory  Inverter – Nucleus of Digital Integrated Electronics  Static CMOS Logic Circuits  Pseudo nMOS Logic Circuits  Pass Transistor Logic Circuits  Dynamic Logic Circuits  Case Studies

3. Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

4. nMOS Pass Transistor – Logic ‘1’ Transfer

5. nMOS Pass Transistor – Logic ‘0’ Transfer

7. PASS TRANSISTORS IN SERIES

8. PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

9. TRANSMISSION GATES  NMOS pass transistor passes a strong 0 and a weak 1.  PMOS pass transistor passes a strong 1 and a weak 0.  Combine the two to make a CMOS pass gate which will pass a strong 0 and a strong 1.

10. TRANSMISSION GATE

11. PROBLEMS WITH TRANSMISSION GATES  No isolation between the input and output.  Output progressively deteriorates as it passes through various stages. However designs get simplified.

12. TRANSMISSION GATE - LAYOUT

13. PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

14. Multiplexor

15. Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

16. XOR gate

17. PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

18. D – Latch

19. TIMING ISSUES

20. D LATCH

21. D - LATCH

22. D LATCH – ALTERNATE CIRCUIT TOPOLOGY

23. PASS TRANSISTOR LOGIC CIRCUITS  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

24. Static Flip Flop 0 1 D 1 0 Q Clk Transparent when Clk=0Transparent when Clk=1 At Clk= 0  1, Q = D. Else Q is held.

25. D Flip Flop – Circuit Diagram

26. D Flip Flop - Operation

27. D Flip Flop - Waveforms

28. Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

29. Handling Clock Skew Clk-in Clk Clk'

30. Pass Transistor Logic Circuits  nMOS Pass transistor – transmission properties  Transmission Gates  Transmission Gate Applications  Mux  XOR  D Latch  D Flip Flop  Clock Skew management  Pass Transistor Logic Families

31. Pass Transistor Logic Families  Complementary Pass Transistor Logic Family  Dual Pass Transistor Logic Family  Swing Restored Pass Transistor Logic Family

32. Problems  Design 4 to 1 multiplexor using transmission-gates.  Implement an XOR gate using minimum number of transistors.  Implement a full adder using transmission gates.

33. Solution - 1 C'0C'0 C0C0 C1C1 C'1C'1 Y A0 A1 A2 A3

34. Solution - 2 C'0C'0 C0C0 C'1C'1 A0 A1 A2 A3 C1C1 Y

35. XOR Gate AB ABAB