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Day 23: November 2, 2012 Pass Transistor Logic: part 2

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Presentation on theme: "Day 23: November 2, 2012 Pass Transistor Logic: part 2"— Presentation transcript:

1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 23: November 2, 2012 Pass Transistor Logic: part 2 (Cascading without Buffers) Penn ESE370 Fall DeHon

2 Previously Penn ESE370 Fall DeHon

3 Two XOR Gates Penn ESE370 Fall DeHon

4 Today Pass Transistor Circuit Transmission gates Tristate gates
Output levels Cascading Series pass transistors? Delay Transmission gates Tristate gates Penn ESE370 Fall DeHon

5 Cascading Pass Transistors
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6 Chain without Inverters
What if we did this? Penn ESE370 Fall DeHon

7 Extract key path Penn ESE370 Fall DeHon

8 t=0 (after Vin transition 10)
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9 t=4t (after Vin transition 10)
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10 t=∞ (after Vin transition 10)
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11 Focus on Pass tr Vgs? Operation mode? Current flow?
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12 Voltage of Chain What is voltage at output?
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13 How compare Compare Penn ESE370 Fall DeHon

14 DC Analysis Penn ESE370 Fall DeHon

15 DC Analysis – chain of 6 Penn ESE370 Fall DeHon

16 Conclude Can chain any number of pass transistors and only drop a single Vth Penn ESE370 Fall DeHon

17 Transient Penn ESE370 Fall DeHon

18 Closeup Penn ESE370 Fall DeHon

19 Capacitance What is Capacitance per stage (@y)?
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20 Delay Delay as a function of chain length?
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21 Compare CMOS Buffered Pass TR Unbuffered Pass TR Delay Area
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22 Pass TR Tree What if we did this? Penn ESE370 Fall DeHon

23 Path What’s different about this? Penn ESE370 Fall DeHon

24 Gate Cascade? What are voltages? Penn ESE370 Fall DeHon

25 Demonstration Circuit
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26 SPICE TODO show spice results of voltages
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27 Demonstration Chain Penn ESE370 Fall DeHon

28 Spice Penn ESE370 Fall DeHon

29 Conclude Cannot cascade degraded inputs into gates.
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30 Midterm 2 Topics Tau-model Logic Elmore-delay Scaling Energy and power
Estimation and optimization Elmore-delay Energy and power Dynamic and static Logic CMOS Ratioed Pass transistor Scaling Noise Margins No clocking Except to motivate delay targets and power calculations Note: 2010 midterm and 2011 midterm2 Penn ESE370 Fall DeHon

31 Time Permitting… Penn ESE370 Fall DeHon

32 Other Gates Penn ESE370 Fall DeHon

33 Other gates What does this do? B A More examples in book.
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34 Pass Rail-to-Rail Penn ESE370 Fall DeHon

35 Transmission Gate Voltage levels at output?
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36 Bus Drivers Penn ESE370 Fall DeHon

37 Tristate Driver Penn ESE370 Fall DeHon

38 Tri-State Drivers Penn ESE370 Fall DeHon

39 Idea There are other circuit disciplines
Can use pass transistors for logic Even chains of pass transistors Sometimes gives area or delay win Do not cascade as easily as CMOS Penn ESE370 Fall DeHon

40 Admin Project Daylight Savings Time change this weekend
Due Saturday Daylight Savings Time change this weekend …get an extra hour to study for… Midterm 2: Nov. 7th Evening Wednesday Penn ESE370 Fall DeHon


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