1. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates

2. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Transistor Sizing

3. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Propagation Delay Analysis - The Switch Model

4. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction What is the Value of R on ?

5. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Numerical Examples of Resistances for 1.2  m CMOS

6. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Analysis of Propagation Delay

7. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design for Worst Case

8. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Influence of Fan-In and Fan-Out on Delay

9. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction t p as a function of Fan-In

10. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques

11. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (2)

12. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (3)

13. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (4)

14. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Example: Full Adder

15. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction A Revised Adder Circuit

16. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Properties of Complementary CMOS Gates

17. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Transistor Sizing

18. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Propagation Delay Analysis - The Switch Model

19. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction What is the Value of R on ?

20. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Numerical Examples of Resistances for 1.2  m CMOS

21. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Analysis of Propagation Delay

22. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Design for Worst Case

23. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Influence of Fan-In and Fan-Out on Delay

24. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction t p as a function of Fan-In

25. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques

26. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (2)

27. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (3)

28. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Fast Complex Gate - Design Techniques (4)

29. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Example: Full Adder

30. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction A Revised Adder Circuit

31. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Ratioed Logic

32. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Ratioed Logic

33. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Active Loads

34. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Load Lines of Ratioed Gates

35. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pseudo-NMOS

36. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Psudo-NMOS –N+1 transistors (small) One pull-up P transistor –Ratio based logic: Sizes Matter –Sensitive to power supply –Static power dissipation: Slow and/or power hungry

37. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pseudo-NMOS NAND Gate V DD GND

38. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Improved Loads

39. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Improved Loads (2)

40. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Example

41. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass-Transistor Logic

42. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction NMOS-only switch

43. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Solution 1: Transmission Gate

44. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass Gate Structures l Bad –Can be slow –Complementary layout is hard to do well –Well plugs are a problem (no vdd/gnd) –Non-standard minimization techniques –True and complement inputs typically needed. l Good –Can be very small – Complementary layout not always used –Non-Boolean logic functions –True switching functions supported –Storage integrated into logic structures

45. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass Logic l NMOS style - accept weak "1"'s –restore good 1's with an inverter l CMOS style -- messy to lay out –wells and well plugs l Precharged / feedback / pseudo-pullup

46. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Resistance of Transmission Gate

47. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass-Transistor Based Multiplexer GND V DD In 1 In 2 SS S S

48. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Transmission Gate XOR

49. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Delay in Transmission Gate Networks

50. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Elmore Delay (Chapter 8)

51. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Delay Optimization

52. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Transmission Gate Full Adder

53. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction (2) NMOS Only Logic: Level Restoring Transistor

54. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Level Restoring Transistor

55. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Solution 3: Single Transistor Pass Gate with V T =0

56. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Complimentary Pass Transistor Logic

57. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction Pass Gate Logic

58. Introduction to VLSI Design© Steven P. Levitan 1998 Introduction 4 Input NAND in CPL