1. Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.
Chapter 5
Static MOS Gate Circuits
Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

2. 5.2 CMOS Gate Circuits

3. 5.2 CMOS Gate Circuits

4. 5.2.1 Basic CMOS Gate Sizing

5. 5.2.1 Basic CMOS Gate Sizing

6. 5.2.1 Basic CMOS Gate Sizing

7. (5.1) (5.2) 5.2.1 Basic CMOS Gate Sizing Equivalent width
series stack :
parallel stack :
(5.1)
(5.2)

8. 5.2.2 Fanin and Fanout Considerations

9. 5.2.2 Fanin and Fanout Considerations
DeMorgan’s Laws
(5.3)

10. 5.2.2 Fanin and Fanout Considerations

11. 5.2.2 Fanin and Fanout Considerations

12. 5.2.2 Fanin and Fanout Considerations

13. 5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

14. 4.6.1 DC Analysis of CMOS Inverter

15. 5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

16. 5.3 Complex cmos gates

17. (5.4) (5.5) 5.3 Complex CMOS Gates Logic function
exchanging AND, OR operations
apply DeMorgans
(5.4)
(5.5)

18. 5.3 Complex CMOS Gates

19. 5.3 Complex CMOS Gates

20. 5.4 xor and xnor Gates

21. 5.4 XOR and XNOR Gates

22. 5.5 Multiplexer Circuits

23. 5.5 Multiplexer Circuits

24. 5.6 Flip-Flops and latches

25. 5.6.1 Basic Bistable Circuit

26. 5.6.1 Basic Bistable Circuit
Average propagation delay
(5.6)

27. 5.6.2 SR Latch
SR Latch with NOR Gates

28. 5.6.2 SR Latch
SR Latch with NAND Gates

29. 5.6.3 JK Flip-Flop

30. 5.6.4 JK Master-Slave Flip-Flop

31. 5.6.5 JK Edge-Triggered Flip-Flop

32. 5.7 D Flip-flops and latches

33. 5.7 D Flip-Flops and Latches

34. 5.7 D Flip-Flops and Latches

35. 5.7 D Flip-Flops and Latches

36. 5.7 D Flip-Flops and Latches

37. 5.7 D Flip-Flops and Latches

38. 5.7 D Flip-Flops and Latches

39. 5.7 D Flip-Flops and Latches

40. 5.8 Power dissipation in CMOS Gates

41. 5.8 Power Dissipation in CMOS Gates
General power equation :
(5.7)

42. 5.8.1 Dynamic (Switching) Power

43. (5.8) (5.9) (5.10) 5.8.1 Dynamic (Switching) Power
Average charging current :
Power dissipation :
(5.8)
(5.9)
(5.10)

44. 5.8.1 Dynamic (Switching) Power

45. (5.11) 5.8.1 Dynamic (Switching) Power Time period :
Average crowbar current :
Average power :
(5.11)

46. (5.12) (5.13) 5.8.1 Dynamic (Switching) Power Average power :
(using switching activity factor )
(5.12)
(5.13)

47. (2.32) (5.14) (5.15) (5.16) 5.8.2 Static (Stanby) Power (in Chapter 2)
(basic diode equation)
Leakage current :
Static power dissipation :
(pseudo-NMOS, low output)
(2.32)
(5.14)
(5.15)
(5.16)

48. (5.17) (5.18) 5.8.3 Complete Power Equation Power equation CMOS gate :
pseudo-NMOS gate :
(5.17)
(5.18)

49. (5.17) (5.18) 5.8.3 Complete Power Equation Power equation CMOS gate :
pseudo-NMOS gate :
(5.17)
(5.18)

54. 5.9 Power and delay tradeoffs

55. (5.19) (5.20) 5.9 Power and Delay Tradeoffs (average power)
(propagation delay)
Power-delay product (PDP)
Capacitor energy
(5.19)
(5.20)

56. (5.21) (5.22) (5.23) 5.9 Power and Delay Tradeoffs
Energy-delay product (EDP)
(propagation delay)
using propagation delay
(5.21)
(5.22)
(5.23)

57. (2.25) 2.5.2 Current Equations for Velocity-Saturated Devices
Linear region operation
(2.25)

58. 2.5.2 Current Equations for Velocity-Saturated Devices
Saturation region operation
Limiting cases :
( )
( )
(2.26)
(2.27)
(2.28)
(2.29)

59. 5.9 Power and Delay Tradeoffs

60. 5.9 Power and Delay Tradeoffs

61. 5.9 Power and Delay Tradeoffs
Optimum EDP :

65. 5.10 Summary

66. 5.10 Summary
Equivalent device width :
Average propagation delay :
Power :
Complete power equation :
(standard CMOS gate)
(pseudo-NMOS gate)
Energy-delay product :