1. EE415 VLSI Design Harris Semiconductor Field Trip to Harris Semiconductor Monday (February 28th) Leave at 9:00 AM from Stocker There will be a class on the 25th!! Will discuss Quiz 3 Tour from ~1:30 PM to 4 PM Arrive in Athens after 8PM Bring cash for food No MAKE-UP please

2. EE415 VLSI Design Read 4.1, 4.2 Start Reading 4.3 (dynamic CMOS) COMBINATIONAL LOGIC

3. EE415 VLSI Design As long as Fan-out Capacitance dominates Progressive Sizing: Can Reduce Delay by more than 30%! Example 4.3: no sizing: t pHL = 1.1 nsec with sizing: t pHL = 0.81 nsec Fast Complex Gate - Design Techniques

4. EE415 VLSI Design Fast Complex Gate - Design Techniques Transistor Ordering

5. EE415 VLSI Design Fast Complex Gate - Design Techniques Improved Logic Design

6. EE415 VLSI Design Fast Complex Gate - Design Techniques Buffering: Isolate Fan-in from Fan-out C L C L Read Example 4.5

7. EE415 VLSI Design Ratioed Logic V DD V SS PDN In 1 2 3 F R L Load Resistive N transistors + Load V OH = V DD V OL = R DN R + R L Asymmetrical response Static power consumption t pLH = 0.69 R L C L V DD

8. EE415 VLSI Design Ratio Based Logic Problems with Resistive Load I L = (V DD – V out) / R L Charging current drops rapidly once V out starts to rise Solution: Use a current source! Available current is independent of voltage Reduces t pLH by 25%

9. EE415 VLSI Design Load Lines of Ratioed Gates

10. EE415 VLSI Design Active Loads

11. EE415 VLSI Design Active Loads Depletion mode NMOS load V GS = 0 I L ~ (k n, load / 2) (|V Tn |) 2 Deviates from ideal current source Channel length modulation Body effect V SB != V DD varies with V out reduces |V Tn |, hence I L for increasing V out

12. EE415 VLSI Design Active Loads Pseudo-NMOS load No body effect, V SB = 0V V GS = - V DD, higher load current I L = (k p / 2) (V DD - |V Tn |) 2 Larger V GS causes pseudo-NMOS load to leave saturation mode sooner than NMOS

13. EE415 VLSI Design Pseudo-NMOS For Vin = V DD : NMOS linear PMOS saturated Read PP 206, 207, Example 4.6

14. EE415 VLSI Design Pseudo-NMOS NAND Gate V DD GND Out

15. EE415 VLSI Design Improved Loads Standby mode reduces power dissipation

16. EE415 VLSI Design Improved Loads (2) Dual Cascode Voltage Switch Logic (DCVSL)

17. EE415 VLSI Design Example B AA B BB Out XOR-NXOR gate

18. EE415 VLSI Design Pass-Transistor Logic I n p u t s Switch Network Out A B B B N transistors No static consumption

19. EE415 VLSI Design NMOS-only switch V TN

20. EE415 VLSI Design Solution 1: Transmission Gate A B C C A B C C

21. EE415 VLSI Design Resistance of Transmission Gate

22. EE415 VLSI Design Pass-Transistor Based Multiplexer GND V DD In 1 In 2 SS S S

23. EE415 VLSI Design Transmission Gate XOR