1. IV UNIT : GATE LEVEL DESIGN
Logic Gates
IV UNIT : GATE LEVEL DESIGN
VLSI Design

2. Logic Gates and Other complex gates
PTL: Pass-Transistor Logic
TGL: Transmission Gate Logic
CPL: Complementary Pass-Transistor Logic
DPL: Differential Pass-Transistor Logic
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4. Pass Transistor Logic(PTL)
Seating chart updates
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5. MOS Pass transistor configurations
Strong 1
Strong 0
Weak 1
MOS Pass transistor configurations
Weak 0
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High Impedance states

6. MOS Pass transistor configurations
NMOS PMOS
G= off on
G= on off
Pass
VDD VDDVTN VDD
VTP
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7. Threshold drops VDD  0 PDN 0  VDD CL PUN VDD 0  VDD – VTn
Strong 1
Weak 1
VDD  0
PDN
0  VDD CL
PUN
VDD
0  VDD – VTn
VDD  |VTp| S D
VGS
Strong 0
Weak 0
Threshold drop: In the case of NMOS, the maximum output is VDD – VT and not VDD, as the transistor switches off when the output reaches this value (Poor “1)
In the case of PMOS, the minimum output is VTp and not 0, as transistor switches off when the output reaches VTp (Poor “0”)
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8. Signal Strength Strength of signal
How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0
nMOS pass strong 0
But degraded or weak 1
pMOS pass strong 1
But degraded or weak 0
Both nMOS and pMOS have voltage degradation problems
nMOS degrades logic ‘1’
pMOS degrades logic ‘0’
Thus nMOS are best for pull-down network
Thus pMOS are best for pull-up network
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9. Pass Transistors Transistors can be used as switches 13/02/2009
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10. Pass Transistors Transistors can be used as switches 13/02/2009
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11. NMOS Pass Transistors We have assumed source is grounded
What if source > 0?
e.g. pass transistor passing VDD
Let Vg = VDD
Now if Vs > VDD-Vt, Vgs < Vt
Hence transistor would turn itself off
NMOS pass transistors pull-up no higher than VDD-Vtn
Called a degraded “1”
Approach degraded value slowly (low Ids)
PMOS pass transistors pull-down no lower than Vtp
Called a degraded “0” Vs
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12. Pass Transistor Ckts
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13. Pass Transistor Ckts
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14. Cascaded NMOS Only Pass Transistors
B = VDD
B = VDD
C = VDD G x y
Out
A = VDD M1 M2
A = VDD M1
x = VDD - VTn1 S G y
Out
C = VDD M2 S
Swing on y = VDD - VTn1 - VTn2
Swing on y = VDD - VTn1
what if C (on right) is VDD-Vtn?
Pass transistor gates should never be cascaded as on the left
Logic on the right suffers from static power dissipation and reduced noise margins
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Neglect Body Effect

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17. NMOS Transistors in Series/Parallel
Primary inputs drive both gate and source/drain terminals
NMOS switch closes when the gate input is high
Remember - NMOS transistors pass a strong 0 but a weak 1 A B
X = Y if A and B X Y A
X = Y if A or B B X Y
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VLSI Design

18. PMOS Transistors in Series/Parallel
Primary inputs drive both gate and source/drain terminals
PMOS switch closes when the gate input is low
Remember - PMOS transistors pass a strong 1 but a weak 0 A B
X = Y if A and B = A + B X Y A
X = Y if A or B = A  B B X Y
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19. Pass Transistor (PT) LogicB B A A F
= A  B B B F
= A  B
The presence of the switch driven by B is essential to ensure that the gate is static – a low-impedance path must exist to supply rails.
Gate is static – a low-impedance path exists to both supply rails under all circumstances
N transistors instead of 2N
No static power consumption
For lecture
what does this implement? (AND gate) how many transistors would it take to implement the same function in static comp CMOS?
at first the switch driven by !B seems to be redundant. It is needed to ensure that a low impedance path exists to the supply rails under all circumstances (when B is low)
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20. Pass-Transistor Logic
(b)
(a) XOR function implemented with pass-transistor circuit, (b) Karnaough map showing derivation of the XOR function
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21. Pass-Transistor Logic
Threshold voltage drop at the output of the pass-transistor gate
Voltage drop does not exceed Vth when there are multiple transistors in the path
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22. NMOS Only Pass Transistor Driving an Inverter
VDD
Vx = VDD-VTn
VGS M2
A = VDD S D B M1
Vx does not pull up to VDD, but VDD – VTn
Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)
Notice VTn increases of pass transistor due to body effect (VSB)
situation is worsened by the body effect since there is SIGNIFICANT source to body voltage when pulling high since the body is tied to GND and the source charges up to VDD
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VLSI Design

23. Voltage Swing of Pass Transistor Driving an Inverter
In = 0  VDD
1.5/0.25 S x D
VDD
Out
0.5/0.25
0.5/0.25 B
situation is worsened by the body effect since there is significant source to body voltage when pulling high since the body is tied to GND and the source charges up to VDD
Body effect – large VSB at x - when pulling high (B is tied to GND and S charged up close to VDD)
So the voltage drop is even worse
Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))
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24. TGL: Transmission Gate Logic
TX Gate
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25. Transmission Gate
A special CMOS circuit that is not available in the other digital logic families is the Transmission Gate.
Essentially an electronic switch, which is controlled by an input logic level
Used for simplifying the construction of various digital components when fabricated in CMOS technology.
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26. Transmission Gate
Maintains the voltage swing of the signal Strong ‘1’ and strong ‘0’.
As there are two channels conducting, the device speed improves.
It is found that the transmission gate has robust characteristics compared to a CMOS gate.
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27. Transmission Gate Can reach 2.5V and 0VB A B C C
C =
2.5 V
Can reach 2.5V
and 0V
A =
2.5 V B C L C
= 0 V
Transmission gate combines the best of both devices by placing an NMOS in parallel with PMOS (most popular approach).
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28. CMOS TX Gate Cross Section
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29. Transmission Gates (TGs)
Most widely used solution C C A B A B C C
C = GND
C = GND
A = VDD B
A = GND B
Use the NOMS to pull down and the PMOS to pull up
Sizing - use all minimum size, increasing W/L has no net impact on switching delay (reduces resistance but increases diffusion capacitance)
Also ratioless logic
C = VDD
C = VDD
Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1
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30. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
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31. Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y X 1X 1
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32. Gate-Level Mux Design How many transistors are needed? 13/02/2009
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33. Gate-Level Mux Design How many transistors are needed? 20 13/02/2009
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34. Transmission Gate Mux Nonrestoring mux uses two transmission gates
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35. Transmission Gate Mux Nonrestoring mux uses two transmission gates
Only 4 transistors
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37. DESIGNING USING TG
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38. XOR by transmission gate
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39. Multiplexer with transmission gate
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40. 13/02/2009
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