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Day 22: October 31, 2011 Pass Transistor Logic

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Presentation on theme: "Day 22: October 31, 2011 Pass Transistor Logic"— Presentation transcript:

1 Day 22: October 31, 2011 Pass Transistor Logic
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 22: October 31, 2011 Pass Transistor Logic Penn ESE370 Fall DeHon

2 Previously Penn ESE370 Fall DeHon

3 Two Xor Gates Penn ESE370 Fall DeHon

4 Today Pass Transistor Circuit Transmission gates Tristate gates
Output levels Cascading Series pass transistors? Delay Transmission gates Tristate gates Penn ESE370 Fall DeHon

5 Cascading Pass Transistors
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6 Chain without Inverters
What if we did this? Penn ESE370 Fall DeHon

7 Extract key path Penn ESE370 Fall DeHon

8 t=0 (after Vin transition 10)
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9 t=4t (after Vin transition 10)
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10 t=∞ (after Vin transition 10)
Penn ESE370 Fall DeHon

11 Focus on Pass tr Vgs? Operation mode? Current flow?
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12 Voltage of Chain What is voltage at output?
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13 How compare Compare Penn ESE370 Fall DeHon

14 DC Analysis Penn ESE370 Fall DeHon

15 DC Analysis – chain of 6 Penn ESE370 Fall DeHon

16 Conclude Can chain any number of pass transistors and only drop a single Vth Penn ESE370 Fall DeHon

17 Capacitance What is Capacitance per stage (@y)?
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18 Delay Delay as a function of chain length?
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19 Compare CMOS Buffered Pass TR Unbuffered Pass TR Delay Area
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20 Pass TR Tree What if we did this? Penn ESE370 Fall DeHon

21 Path What’s different about this? Penn ESE370 Fall DeHon

22 Gate Cascade? What are voltages? Penn ESE370 Fall DeHon

23 Demonstration Circuit
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24 SPICE TODO show spice results of voltages
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25 Demonstration Chain Penn ESE370 Fall DeHon

26 Spice Penn ESE370 Fall DeHon

27 Conclude Cannot cascade degraded inputs into gates.
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28 Pass Rail-to-Rail Penn ESE370 Fall DeHon

29 Transmission Gate Penn ESE370 Fall DeHon

30 Bus Drivers Penn ESE370 Fall DeHon

31 Tristate Driver Penn ESE370 Fall DeHon

32 Tri-State Drivers

33 Admin Project Midterm 2: Nov. 9th Due Friday
Week from today in the evening Penn ESE370 Fall DeHon

34 Midterm Topics Scaling Logic Tau-model Elmore-delay No clocking
Estimation and optimization Elmore-delay Energy and power Logic CMOS Ratioed Pass transistor No clocking Except to motivate delay targets and power calculations Note: 2010 midterm Q4 – Cdiff, trans gates, Elmore, opt. Penn ESE370 Fall DeHon

35 Idea There are other circuit disciplines
Can use pass transistors for logic Even chains of pass transistors Sometimes gives area or delay win Do not cascade as easily as CMOS Penn ESE370 Fall DeHon


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