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ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher.

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Presentation on theme: "ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher."— Presentation transcript:

1 ELEC 5270/6270 Spring 2011 Low-Power Design of Electronic Circuits Pass Transistor Logic: A Low Power Logic Family Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

2 Low-Power Logic Styles
Pass transistor logic Dynamic logic Domino logic Adiabatic and charge recovery logic Asynchronous logic Logic restructuring Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

3 Pass Transistor Logic (PTL)
Requires fewer transistors Smaller area Reduced capacitance Reduced energy and power Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

4 CMOS AND Gate A F = AB B A F = AB B Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 12

5 Pass Transistor AND Gate
B A F = AB Need 4 transistors instead of 6 for CMOS AND gate. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

6 CMOS OR Gate A B F = A + B A F = A + B B Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 12

7 Pass Transistor OR Gate
B 1 F = A + B A Need 4 transistors instead of 6 for CMOS OR gate. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

8 Reduced Voltage Swing IN Vx = VDD – Vtn OUT VDD = 2.5V
n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

9 Spice Simulation 3.0 IN 2.0 1.0 Voltage, V Vx 0.0 OUT
Time, ns J. M. Rabaey, A. Chandrakasan and B. Nokolić, Digital Integrated Circuits, Upper Saddle River, New Jersey: Pearson Education, 2003. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

10 Voltage Transfer Characteristic (VTC) of AND Gate
B A F = AB n transistors, W/L = 0.5μ/0.25μ p transistors, W/L = 1.5μ/0.25μ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

11 VTC: Spice Simulation 3.0 2.0 VDD – Vtn 1.0 B = VDD A = 0 → VDD 0.0
F, V A = VDD, B = 0 → VDD A = B = 0 → VDD Vin, V Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

12 Energy 0 → VDD Vout VDD = 2.5V i(t) CL T T
If this voltage is insufficient for turning the pMOS Transistor in inverter off, leakage power will be consumed. 0 → VDD Vout VDD = 2.5V i(t) CL T T E0→ = ∫ P(t) dt = VDD ∫ i(t) dt VDD-Vtn = VDD ∫ CL dVout = CL VDD (VDD – Vtn) < CL VDD2 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

13 Energy: PTL vs. CMOS PTL consumes less dynamic power than static CMOS Logic. PTL leakage may be higher when output is low, because the reduced voltage level may be insufficient to turn the PMOS transistor in the inverter off. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

14 Ways to Reduce Leakage Level restoration
Multiple-threshold transistors Transmission-gate logic Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

15 Level Restoration VDD Level restorer B=1 Vout A=1 CL
CL Level restorer device should be weaker than the nMOS pass transistor. Otherwise, VDD → 0 transition at Vout will be impossible. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

16 Multiple-Threshold Transistors
Use zero-threshold pass-transistors. Use high-threshold transistors in all other gates. This can cause leakage through multiple gates. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

17 Leakage Through Zero-Threshold Transistors
1 Zero or low-threshold transistors Leakage current path 1 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

18 Transmission-Gate Logic
Provides both power and ground levels. Good design, except needs more transistors. Inverting multiplexer A S B S’A’ + SB’ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

19 Transmission-Gate XOR
B AB’+A’B A Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

20 A Logic Library Cell Number of transistors CMOS TGL OR02 6 MUX21 12
AND02 XOR2 AND03 8 AOI32 10 OAI21 OAI32 AO21 NOR04 OR03 NOR02_2x 4 OAI221 NAND02_2x AOI321 INV02 2 DFFR 34 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

21 Synthesis of PTL Shannon’s expansion: Z = AB + BC + AC
= A(B+BC+C) + A’(BC) = A(B+C) + A’BC = A[B+B’C] + A’[BC] A B C Z 1 1 C C B A Z Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

22 Pass-Transistor Cell Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 12

23 Synthesis of Z = A’B + B’C + A’C’
B C = 1, Z = A’B + B’ B = 1, Z = A’ B = 0, Z = 1 C = 0, Z = A’ C Z Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

24 Synthesis of Z = A’ + BC’ + B’C
C C’ B B’ A A’ A = 1, Z = BC’ + B’C B = 1, Z = C’ B = 0, Z = C A = 0, Z = 1 Z Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

25 Synthesis of Z = AB’C’ + A’B’C
C’ C 1 A’ A B’ B A = 1, Z = B’C’ B = 1, Z = 0 B = 0, Z = C’ A = 0, Z = B’C B = 0, Z = C Z Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

26 CPL: Complementary Pass-Transistor Logic
Every signal and its complement is generated. Gates are static, because the output is connected to either VDD or GND. Design is modular; same cell can produce various gates by simply permuting the input signals. Also called differential pass-transistor logic (DPL) Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

27 A CPL Cell Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

28 CPL Cell Used As AND/NAND
B B’ A B A’ B’ Z = AB Z’ = (AB)’ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

29 CPL Cell Used As OR/NOR B’ B A B A’ Z = A + B Z’ = (A + B)’ B’
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

30 CPL Cell Used As XOR/XNOR
B’ B A A’ A’ A Z = AB’ + A’B Z’ = AB + A’B’ Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

31 CPL vs. CMOS CPL requires fewer transistors.
Useful for modular (array) circuits like adders, multipliers, barrel shifter, etc. CPL operation can be faster and energy efficient. Following example is taken from: M. E. Elrabaa, I. S. Abu-Khater, and M. I. Elmasry, Advanced Low-Power Digital Circuit Techniques, Springer, 1997, Chapter 2. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

32 Example: 4-Bit Carry Select Adder
A_ B_1 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_ B_2 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_ B_3 Adder cell S1’ S0’ C0’ C0 C1’ C1 A_ B_4 Adder cell S1’ S0’ C0’ C0 C1’ C1 M M M M M M M M M M M M M M M M M M M M C’_2 C’_4 C_4 C’_0 C_0 S_1 S_2 S_3 S_4 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

33 CMOS Carry-Select Adder Cell
Ai Bi S1’ S0’ C0’ C0 C1’ C1 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

34 CPL Adder Cell Ai Bi S1’ S0’ C0’ C0 C1’ C1 Copyright Agrawal, 2007
ELEC6270 Spring 11, Lecture 12

35 CPL Multiplexer Cell in1 in2 M Ci Ci out Ci’ Ci’ in1 in2
Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

36 32-Bit Adders in 0.8μ, 3.3V Type of design Type of logic Energy μW/MHz
Delay ns Minimum transistor size CMOS 90.0 11.0 CPL 65.0 10.0 Transistor sizing for delay optimization 93.0 10.5 72.0 7.5 Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

37 References G. R. Cho and T. Chen, “On the Impact of Technology Scaling on Mixed PTL/Static Logic,” Proc. IEEE Int. Conf. Computer Design, 2002. R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic,” IEEE J. Solid State Circuits, vol. 32, no. 7, pp , July 1997. Copyright Agrawal, 2007 ELEC6270 Spring 11, Lecture 12

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