1. Digital Integrated Circuits for Communication
Every Wednesday:
15:00 hrs to 18:00 hrs
هر اربع:
شام 3 وڳي کان 6 وڳي تائين
Digital Integrated Circuits for Communication
احسان احمد عرساڻِي

2. My Introduction منهنجو تعارف
Ahsan Ahmad Ursani
Associate Professor
Dept. of Telecommunication Engineering
Office No: TL-117
Institute of Communication Technologies
Web page:
احسان احمد عرساڻي
ايسوسيئيٽ پروفيسر
شعبو ڏور ربطيات
دفتر نمبر: TL-117
انسٽيٽيوٽ آف ڪميونيڪيشن ٽيڪنالاجيز
برق ٽپال:
ويب صفحو:

3. The Teaching Plan تدريسي رٿا
Pre-Requisite: IC Design
S. No.
Chapter
Hours 1
Dynamc Combinational CMOS Logic 10 2
Designing Sequential Logic 17 3
Designing Memory and Array Structures 21
Total 48

4. The Textbook نصابي ڪتاب
Digital Integrated Circuits
A Design Perspective
Jan M. Rabaey
Chapter 6, 7, & 12

5. Chapter 1 باب پهريون S. No. Topic Hours 1 Introduction 2
Complementary CMOS 3
Ratioed Logic 4
Pass-Transistor Logic 5
Basic Principles of Dynamic Logic 6
Speed and Power Dissipation 7
Issues in Dynamic Design 8
Casdaing Dynamic Gates 9
Choosing a logic Design 10
Designing logic for Reduced Supply Voltages
Total

6. Static Vs Dynamic
Static
Dynamic
At every point in time (except during the switching transients) each gate output is connected to either VDD or Vss via a low-resistance path.
the outputs of the gates assume at all times the value of the Boolean function implemented by the circuit (ignoring, once again, the transient effects during switching periods).
Relies on temporary storage of signal values on the capacitance of high- impedance circuit nodes

7. Static Vs. Dynamic
Static
Dynamic

8. Basic concepts of a dynamic gate
An n-type network
AB+C Gate

9. Dynamic Logic – Basic Principle
Uses N+2 transistors
N is the no. Of inputs
Uses clock cycle
Two phases
Pre-Charge
Pre-charge PMOS conducts
Doesn’t implement logic during the pre-charge phase
Evaluation
Evaluation NMOS conducts
Pre-Charge
Unconditionally Charges out to 1 through Mp
Evaluation
Logically discharges out to 0 through Me and PDN

10. Properties of Dynamic Logic
Advantages
Disadvantages
Faster than Static CS CMOS logic
Less power consumption than ratioed logic
No care in transistor sizing for proper functionality
Glitching (or dynamic hazards) does not occur in dynamic logic
More power consumption than Static CS CMOS logic
There’s a Dead Zone
Dynamic logic gates cannot be used during pre-charge phase

11. Power Consumption in Dynamic Logic
Non-ratioed logic
No static power consumption
Only dynamic power consumption
During transitions
Depends on the switching activity
α01 = P0P1
α01 = P0(1)
α01 = P0
α01 = N0 /2N
N is the number of inputs
There are 2N combinations in the TT
N0 is the no. of zeros in the TT

12. Problem 6.7: Activity Computation Page 278
For the 4-input dynamic NAND gate, compute the activity factor with the following assumption for the inputs.
Assume that the inputs are independent and
pA=1 = 0.2,
pB=1 = 0.3,
pC=1 = 0.5, and
pD=1 = 0.4. A B C D Y 1

13. Comparing 2-input NOR Gates
Switching Activity
Truth Table
Static
α01 = P1 P0 = ¼ ¾ = 3/16
Dynamic
α01 = P0 = ¾ A B Y 1

14. 4-input NAND gate

15. Characteristics of 4-input Dynamic Gate
VOL = 0V
VIL = VTN
NML = VTN
tpLH = 0 ns
tpre = nsec
VOH = VDD
VIH = VTN
NMH = VDD – VTN
tpHL = 0.11 ns
Proportional to the no. Of NMOS in PDN
VM = VTN

16. Pre-charge time Pre-charge time is a ‘Dead Zone’ Doesn’t apply logic
It is the time proportional
to the charging time CL
Inversely proportional to the width of the pre- charge PMOS
Mp wider
Less resistance
Less charging time
Too large Mp might be slowdown the gate and increase the power dissipation of the clock signal
May coincide with other system functions

17. Basic concepts of a P-type dynamic gate
A p-type network
AB+C Gate

18. Issues in Dynamic Design
Charge Leakage
Charge Sharing
Capacitive Coupling
Clock-Feedthrough

19. Charge Leakage

20. Periodic refresh
Lower bound on operating frequency

21. Solution
Bleeder transistor

22. Charge Sharing During precharge During evaluation A=B=0
Ca s discharged
During evaluation
A makes 01 transition while B=0
Ma turns ON
The charge stored originally on capacitor CL is redistributed over CL and Ca
This causes a drop in the output voltage

23. Charging sharing in 3-i/p XNOR
Pre-charge
A=0, B=0, C=0
Evaluation
A=0, B=1, C=1
VDD =2.5 v

24. Solution to Charge Sharing
Precharging critical internal internal nodes
The most common and effective approach to deal with the charge redistribution
comes at the cost of increased area and capacitance.

25. Capacitive Coupling High o/p impedance Backgate coupling floating node
very sensitive to crosstalk effects
A wire routed over a dynamic node may couple capacitively
Backgate coupling
O/p to i/p coupling

26. Capacitive Coupling High o/p impedance Backgate coupling floating node
very sensitive to crosstalk effects
A wire routed over a dynamic node may couple capacitively
Backgate coupling
O/p to i/p coupling

27. Clock-Feedthrough
CC b/w Clock i/p of Preharge device and Dynamic o/p node

28. Cascading Dynamic Gates

29. Designing Logic for Reduced Supply Voltages

30. Problem 6.7 Activity Computation
For the 4-input dynamic NAND gate, compute the activity factor with the following assumption for the inputs. Assume that the inputs are independent and PA=1 = 0.2, PB=1 = 0.3, PC=1 = 0.5, and PD=1 = 0.4.