1. EENG447
Digital IC Design
Dr. Gürtaç Yemişcioğlu

2. CHAPTER #2 CAD TOOLS & DESIGN ENTRY Schematic Fundamentals 17/01/2019
Digital IC Design

3. SCHEMATIC FUNDAMENTALS
Logic circuits are built with transistors. Transistors is the smallest building block or device. Transistor operates as a simple switch.
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Digital IC Design

4. SCHEMATIC FUNDAMENTALS
The most popular type of transistor for implementing a simple switch is the Complementary Metal Oxide Semiconductor (CMOS). In CMOS there are two types of transistors, PMOS and NMOS and together they complement each other.
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Digital IC Design

5. SCHEMATIC FUNDAMENTALS
DEVICES
NMOS
PMOS
x = “high”/ “1”
x = “low”/ “0”
x = “low”/ “0”
x = “high”/ “1”
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Digital IC Design

6. SCHEMATIC FUNDAMENTALS
DEVICES
NMOS
PMOS VD
VD = 0 V VD
VS = VDD
VDD
VG = VDD
VG = vDD
VS = 0V VD VD
VD = VDD
Closed switch when VG = VDD
Open switch when VG = 0
Closed switch when VG = 0V
Open switch when VG = VDD
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Digital IC Design

7. SCHEMATIC FUNDAMENTALS
A simpler way to visualise the operation of the transistors is a resistor when it is ON. The amount of current that flows through the transistor is limited by the equivalent resistance of the transistor.
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Digital IC Design

8. SCHEMATIC FUNDAMENTALS
The first schemes for building logic gates with MOSFETs became popular in the 1970s and relied on either PMOS or NMOS transistors, but not both. Since the early 1980s, a combination of both NMOS and PMOS transistors has been used.
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Digital IC Design

9. SCHEMATIC FUNDAMENTALS
NMOS CIRCUITS
When Vx = 0 V, the NMOS is OFF. No current flows through the resistor R, and Vf = 5V. When Vx = 5 V, the NMOS is ON Pulls Vf to a low voltage level.
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Digital IC Design

10. SCHEMATIC FUNDAMENTALS
The exact voltage level of Vf in this case depends on the amount of current that flows through the resistor and transistor. If Vf is viewed as a function of Vx, then the circuit is an NMOS implementation of a NOT gate. The purpose of the resistor in the NOT gate circuit is to limit the amount of current that flows when Vx = 5V. Rather than using a resistor for this purpose, a transistor is normally used.
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Digital IC Design

11. SCHEMATIC FUNDAMENTALS
NMOS CIRCUITS
If Vx1 = Vx2 = 5 V, both transistors will be ON. Vf will be close to 0V. If either Vx1 or Vx2 is 0, then no current will flow through the series-connected transistors. Vf will be pulled up to 5V.
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Digital IC Design

12. SCHEMATIC FUNDAMENTALS
NMOS CIRCUITS
If either Vx1 or Vx2 is 5 V, then Vf will be close to 0V. If both Vx1 = Vx2 = 0 V, then Vf will be pulled up to 5 V.
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Digital IC Design

13. SCHEMATIC FUNDAMENTALS
For each of the circuits that has been presented, it is possible to derive an equivalent circuit that uses PMOS transistors. But it is more interesting to consider how both NMOS and PMOS transistors can be used together. In NMOS circuits the logic functions realised by arrangements of NMOS transistors, combined with pull-up device that acts as a resistor.
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Digital IC Design

14. SCHEMATIC FUNDAMENTALS
The part of the circuit that involves NMOS transistors is known as pull-down network (PDN). The concept of CMOS circuits is based on replacing the pull-up device with a pull-up network (PUN) that is built using PMOS transistors.
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Digital IC Design

15. SCHEMATIC FUNDAMENTALS
The functions realised by the PDN and PUN networks are complements of each other. Then a logic circuit can be implemented . For any given valuation of the input signals, either PDN pull Vf down to Gnd or the PUN pulls Vf up to VDD. The PDN and the PUN have equal number of transistors, which are arranged so that the two networks are duals of one another. Wherever the PDN has NMOS transistors in series, the PUN has PMOS transistors in parallel, and vice versa.
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Digital IC Design

16. SCHEMATIC FUNDAMENTALS
INVERTER
The inverter is the simplest logic gate. Its function is to invert the signal received on the input node to the opposite polarity to the output node. CMOS logic by its very own nature is always inverting. The NMOS and PMOS are never “ON” at the same time. This is why CMOS is a low-power style of circuit design. Once the gate switches state, there is no DC current path between VDD and GND
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Digital IC Design

17. SCHEMATIC FUNDAMENTALS
INVERTER
VDD
P1 = off
P1 = on
x = 0
x = 1
f = 1
f = 0
N1 = on
N1 = off
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Digital IC Design

18. SCHEMATIC FUNDAMENTALS
NAND Gate
VDD x1 x2 x1 x2
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Digital IC Design

19. SCHEMATIC FUNDAMENTALS
AND Gate ?
Draw, 2 – input AND gate Schematic Diagram.
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Digital IC Design

20. SCHEMATIC FUNDAMENTALS
NOR Gate
VDD x1 x2 x1 x2
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Digital IC Design

21. SCHEMATIC FUNDAMENTALS
OR Gate ?
Draw, 2 – input OR gate Schematic Diagram.
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Digital IC Design

22. SCHEMATIC FUNDAMENTALS
XOR Gate ?
Draw, 2 – input XOR gate Schematic Diagram.
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Digital IC Design

23. SCHEMATIC FUNDAMENTALS
Complex Circuits
F = ((A+B+C)D)’
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Digital IC Design

24. SCHEMATIC FUNDAMENTALS
Complex Circuits
F = A’+(B’+C’)D’
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Digital IC Design

25. SCHEMATIC FUNDAMENTALS
Transmission Gates
This configuration allows for noninverting propagation of the input signal, blocking of the input signal when both control signals disabled the PMOS and NMOS transistors.
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Digital IC Design

26. SCHEMATIC FUNDAMENTALS
Transmission Gates
PMOS transistors are connected to generate logical “1” levels and NMOS logical “0” and almost never reverse the reverse. in A B
out 0* 1 X 1*
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Digital IC Design

27. SCHEMATIC FUNDAMENTALS
Transmission Gates
*PMOS transistors are able to pass “0” levels, but degrade the “0” level (weak 0). NMOS transistors are able to pass “1” levels, but degrade “1 level” (weak 1). in A B
out 0* 1 X 1*
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Digital IC Design

28. SCHEMATIC FUNDAMENTALS
Transmission Gates
Usually both controls are implemented such that the transmission gate is either completely “ON” or “OFF” (both transistors) but not halfway. in A B
out 0* 1 X 1*
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Digital IC Design

29. SCHEMATIC FUNDAMENTALS
XOR Gate_v2 ?
Draw, 2 – input XOR gate Schematic Diagram Using Transmission Gate.
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Digital IC Design

30. SCHEMATIC FUNDAMENTALS
XNOR Gate ?
Draw, 2 – input XNOR gate Schematic Diagram Using Transmission Gate.
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Digital IC Design

31. SCHEMATIC FUNDAMENTALS
2-to-1 MUX ?
Draw, 2-to-1 MUX Schematic Diagram Using Transmission Gate. S Y D0 1 D1
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Digital IC Design

32. Thank You!
Any Question?
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Digital IC Design