® SPARTAN Series High Volume System Solution

® Spartan/XL Estimated design size (system gates) 30K 5K180K XC4000XL/A XC4000XV Virtex S05/XL S10/XL S20/XL S30/XL S40/XL 4013XL/A 4020XL/A XL/A..4085XL/A XCV50 XCV100 XCV150 XCV200 XCV300...XCV /3.3 Volts2.5 Volts3.3 Volts/2.5Volts 1M 40110XV XV FPGA Focus Products for New Designs Select Family Based on Density

® Xilinx 4000 Heritage Total Cost Management Advanced Process Technology Smallest die size Low cost packaging Low test cost 100 MHz+ performance On-chip SelectRAM Software and cores Xilinx Spartan Series FPGAs

® Spartan/XL Product Matrix CS packages available only in SpartanXL family

® What you want from a high-volume FPGA solution Family Highlights  Spartan (5.0 Volt) family introduced in Jan. 98 —Fabricated on advanced 0.5µ process technology  Spartan-XL (3.3 Volt) family introduced in Nov. 98 —Fabricated on advanced 0.35µ process technology —Power management features —Higher performance over Spartan (5.0 Volt) —Entire family of 5 devices under $7.50  Both families offer: —SRAM technology (re-programmable) —Leverage industry standard XC4000 architecture —Lowest cost FPGA families with memory (SelectRAM) —Extensive core support —Broadest density/package/temperature/speed offering

® Spartan-XL: More for Less  More: —Faster performance –Speed grades now -4/-5 –Spartan-XL -4x faster than Spartan -4 –Fastest speed grade delivers 100+ MHz performance —Programmable I/O options –Output drive and voltage termination (PCI) –Input latch and output tri-state control register —Parallel express mode configuration  For Less: —Power-down mode (< 100  A typical) –Ideal for high volume portable applications –No sacrifice in performance —Lower prices –Competitive with gate arrays at similar I/O counts

® * ICC PD will be dependent on VCC, junction temperature, and part size Spartan-XL: Power Down Mode  Two power-down modes (ICC PD < 100 mA*) —Power-down pin –Stops clocks –Disables all output pins –Pulls all inputs low –Asserts Global Set/Reset (resets all flip-flops) —Customer power-down –Customer stops clocks –Customer brings input pins to rails guaranteeing logic stops switching –Customer disables I/Os 100uA Full Power

® Faster Time to Market = $ Advantages over ASICs  No costly NRE charges —Standard product  No vector file needed —Devices 100% tested by Xilinx  In system verification vs. simulation —Saves valuable design time  In-field upgradable —Enabler for product differentiation —Allows additional revenue path for end product  Lower material handling cost

® I/O 1998 Gate array, 0.5u, 50K gates Spartan-XL, 0.35u, 20K gates Gate Array 0.8u, 10K gates FPGA 1.0u, 5K gates I/O Spartan/XL FPGAs Match Gate Array Die Size and Cost  FPGAs cannot compete with gate arrays —Older process than ASICs —Larger die —Not I/O pad-limited  FPGAs compete —FPGAs are fab process drivers, replace DRAMs —Competitive die size with similar number of I/O

® System Gates I/Os Gate Array Territory High Density, Low I/O Spartan FPGAs Low Density, High I/O Spartan-II Spartan/XL Spartan Series Replaces Low-Density Gate Arrays

® 100K unit volume price projections K 20K 40K 100K unit volume price projections 30K 40K 200K 100K 10K Gates Per Dollar in 1999! $10 $5 High-Volume Price Leadership

® Focus: High Volume Customer Complete, Ready-to-Use Programmable Logic Design Solution Xilinx Software Solutions Focus: High Density Designers Integrated into the Customer’s Chosen EDA Environment

® Standard Bus Interface Products Peripheral Component Interconnect Bus (PCI) Other Standard Bus Products Digital Signal Processing Correlators Filters Transforms DSP Building Blocks Spartan Core Advantages: Pre-verified in silicon Much lower cost than ASIC cores Simple distribution and licensing Spartan Series Core Support Communications & Networking Products Asynchronous Transfer Mode Forward Error Correction Base-Level Products Basic Elements Math Functions RISC CPU Cores 8-bit RISC Core Processor Peripherals UARTs Others

® Core Function XCS30XL Price Percentage of Device Used Effective Function Cost UART $ % $ bit RISC Processor $ % $ bit, 16-tap Symmetrical FIR Filter $ % $1.49 Reed-Solomon Encoder $5.50 6% $0.33 PCI Interface $ % $2.95 *Prices are for 250K units, plastic package Effective Function Cost with Spartan

® External PLD 15K Gates Component Cost 100K Units Standard Chip PCI Master I/F $5 $15 $20 $10 Standard Chip Solution >$20 PCI Master I/F User Design 15K Gates Xilinx PCI Solution <$10.00 *Prices are for 100K units, plastic package, 3.3v technology Costs Less Than Standard ICs!

® High Volume SPROMs  XC17Sxx SPROMs —Lowest priced SPROM in the industry —Priced to be competitive along with Spartan FPGAs against ASIC and FPGA competition —SPROM volume pricing < 25% of the FPGA  All Spartan family SPROMs in production

® Summary  Xilinx has changed the rules! —Gates-only solutions are no longer required —No more compromises  Spartan Series delivers key ASIC requirements —High Performance (100+ MHz system clocks) —On-chip distributed SelectRAM —Low power and power-down mode —Extensive core support —Low prices competitive with ASICs