1. Xilinx Spartan Series High Performance, Low Cost FPGAs with on-chip SelectRAM Memory

2. Spartan FPGAs ? Xilinx 4000 Heritage Total Cost Management Advanced Process Technology 80 MHz Performance On-chip SelectRAM Software and cores Smallest die size Low packaging cost Low test cost

3. Xilinx Spartan Families  Complete High Volume FPGA Solution SpartanXL: 3.3 Volt with up to 40K System Gates Gates-only solutions are no longer required  Process technology leap UltraDense TM 0.35  m for 3.3 Volt SpartanXL Family  Spartan Series delivers key ASIC requirements with all the FPGA advantages Powerful software tools Most successful FPGA architecture  No compromises Performance, RAM, Cores, and Low Price

4. XCS##XL -3PC84C XCS = Spartan XL = 3.3 Volt no XL = 5 Volt ## = System Gates Spartan Naming  Spartan part name uses “System Gates” Includes both RAM and Logic –High end of current published gate range Matches ASIC industry terminology Consistent with future FPGA families

5. Performance 5200 4000E Spartan/XL (5V/3.V) E-1 E-2 S-4 S-3 -4 -3 Spartan Speed Grades  Higher speed grade = higher performance

6. Spartan Meets ASIC Requirements Low Price Unit Cost Development Cost Unit Cost Development Cost NRE Lost Opportunity Cost of Ownership Per Unit ($) FPGAASIC FPGA Cost of Ownership Advantage No test vectors required Limited or no simulation Automatic Place and Route Re-spins in hours not months Faster Time-to-Market No NRE 1x1x 2x2x 10x

7. Total Cost Management  Leading edge process technology Smallest die size  Streamlined feature set Synchronous single/dual-port Select-RAM Popular serial configuration modes JTAG support  Optimized manufacturing test flow for low cost  Focused package offering Highest volume plastic PLCC, VQ, TQ, PQ, BGA packages

8. UltraDense TM Process Chip Transistor gates 0.5/0.35  - allows 5V/3.3 V supply All other features 0.35/0.25  - small size - low capacitance - performance - low power Combines 5V/3.3 V operation with 0.35/0.25  benefits

9. UltraDense TM Process Core core-limited I/O pads Gate count determines die size Spartan Die Size for High I/O package Nearly Equivalent to Gate Arrays pad-limited Core I/O pads I/O count determines die size

10. Advanced Process Technology eliminates the “RAM compromise” Die Size without RAM 1.0 Logic and RAM I/O pads Die Size with RAM 1.0 Logic Empty, wasted die area Technology advances have reduced die size faster than pad technology

11. Simple Packaging  Focus on popular, low-cost packages Highest-volume ASIC plastic packages  Only six packages: PC84 (05/10) VQ100 (05/10/20/30) TQ144 (10/20/30) PQ208 (20/30/40) PQ240 (30/40) BG256 (30/40)  Optimized PQ208 pinout Adds more I/O

12. Spartan-XL FPGAs Marc Baker 2-High_Volume-8am

13. Spartan-XL Global Buffers  8 BUFGLS buffers Similar to XC4000X Available in new SpartanXL library (M1.5)  BUFGP/BUFGS from a Spartan design get converted automatically  No BUFGE/BUFFCLK

14. Spartan-XL Fast Capture Latch  IOB fast capture latch supported in silicon and software SpartanXL library includes ILFFX, etc.  Note that there is still only one type of clock buffer

15. Spartan-XL CLB Latch  CLB flip-flops can be used as latches  LD, etc. components in SpartanXL library  Simplifies use of HDL synthesis  Similar to XC4000X

16. Spartan-XL Interconnect  Carry only propagates upward Significantly higher speed –Similar to XC4000X Standard long line can be used to continue at the bottom of the next column  Datasheet figure shows upward carry only Text describes that it is bidirectional in the 5V Spartan family  All other device routing is identical to 5V Spartan family

17. Any 5 V device SpartanXL FPGA Advanced 0.35  3.3V Core 3.3V I/O 5V5V 3.3V 5V5V Meets TTL Levels Spartan-XL Family Voltage Compatibility  Spartan inputs accept 5V signals  Spartan outputs drive standard TTL  100% compatible in 5 volt environment

18. Optional 3.3V Clamp for PCI  Programmable global clamp to 3.3V for PCI No V TT pins required BITGEN option –Default is “5V Tolerant I/Os” Similar to XC4000XLA

19. Spartan-XL Output Drive  Programmable 12 mA or 24 mA output drive Pin-by-pin option Default is 12 mA Similar to XC4000XLA

20. Spartan-XL Boundary Scan  M2 pin taken out of scan chain BSDL files are different than 5V Spartan  Added IDCODE Instruction Becomes default instruction  Simplified configuration via boundary scan No need to hold INIT Can abort and retry  Similar to XC4000XLA

21. Spartan-XL Power Down  Former M2 pin has a power-down function Active-low with default pull-up  Disables I/O and OSC, asserts GSR Can be asserted before configuration  After power down is removed, GSR and input disable are removed before outputs are enabled  Cannot lower VCC during power-down  Power down current not yet characterized

22. Spartan-XL Factory Test Input  Former M1 pin is still a “Don’t Connect”  Enables Express Mode configuration for factory testing Default pull-up prevents Express mode

23. SpartanXL (3.3V)Production XCS05XLNow XCS10XLNow XCS20XLNow XCS30XLNow XCS40XLNow Spartan-XL Family Available  Production volumes Now  Spartan-XL software support in 1.5

24. Spartan Series Footprint Compatibility 5 VoltXCS05XCS10XCS20XCS30XCS40 3.3 VoltXCS05XLXCS10XLXCS20XLXCS30XLXCS40XLPC84 VQ100VQ100VQ100VQ100 TQ144TQ144TQ144 PQ208PQ208PQ208PQ240BG256 oHighest volume ASIC plastic packages oFootprint compatible in common packages

25. Xilinx Spartan Series 5 Volt ->XCS05XCS10XCS20XCS30XCS40 3.3 Volt ->XCS05XLXCS10XLXCS20XLXCS30XLXCS40XL System Gates 2K-5K3K-10K7K-20K10K-30K13K-40K Logic Cells23846695013681862 Max Logic Gates 3,0005,00010,00013,00020,000 Flip-Flops 360616112015362016 Max RAM bits 3,2006,27212,80018,43225,088 Max I/O 80112160192224 Performance 80MHz80MHz80MHz80MHz80MHz No Compromises: Performance, RAM, Cores, and Low Price

26. Xilinx Solution for PC99 in PCs and Peripherals Processor Personal Computer Peripherals SpartanXL USB interface/ FireWire interface Device Bay Memory XC9500XL SDRAM Controller USB, FireWire interfaces USBFireWire

27. FPGA Challenge (FireWire Example)  FireWire part of PC99 spec is used to demonstrate the benefits of Xilinx FPGAs  IEEE 1394 standard based on Apple’s original definition of FireWire  High speed serial bus 400 Mbits/s required for PC99; increasing to 3.2 Gbits/s  For emerging consumer electronics digital camcorders, DVD players, digital VCRs, HDTV, set-top boxes, video conferencing  For traditional PC peripherals hard drives, printers, scanners, modems

28. Physical Layer Physical Layer 400 MHz FireWire Receive 50 MHz Link Layer Interface FireWire Link Layer Interface Transmit Section Transmit 8 Application Interface CRC Cycle Start Core State Machine FIFOs Request/ Data PHY Interface  Physical layer operates at full 400 MHz data transfer rate serial-to-parallel conversion drops data rate to 50 MHz for back-end link layer  Link Layer includes CRC generation and FIFOs

29. Challenges Facing the Design Engineer Design complexity Flexibility for an evolving standard Design cycle time HDL entry Cost control High performance FIFOs Design time Design tools Low power

30. Potential Solutions  Discrete logic not practical approach any longer few available 3.3V/2.5V devices available  Chip sets few available expensive  Custom ASIC long design cycle costly to rework  Programmable Logic

31. Spartan-XL Provide Solution Reprogrammable: instant updates Flexibility and design complexity — feature-rich programmable architecture High performance: >100 MHz parallel logic Design tools — established, easy-to-use development tools — complete software support and extensive cores (IP) Cost control — advanced process technology for small, low cost die — streamlined manufacturing provides total cost management

32. Reprogrammability  Fast time to market immediate design changes no cost penalty for mistakes and updates  Immediate production no conversion costs off-the-shelf no inventory risk  100% tested streamlined Xilinx testing reduces costs

33. High Performance FIFOs Using SelectRAM Memory  Any logic block can be used as SelectRAM memory  Distributed RAM provides high performance solutions  Features synchronous write, asynchronous read separate read port in dual-port mode for FIFOs

34.  All Xilinx FPGAs minimize power by using segmented interconnect  3.3V SpartanXL FPGAs consume less than half the power of 5V Spartan FPGAs  Power Down mode reduces quiescent current to 100  A SpartanXL Low Power Spartan Spartan XL Power Down

35. Spartan-XL Implementation  Implement FIFO part of FireWire design as an example  50 MHz required

36. Spartan-XL Benefits  Fast time-to-market user programmable  Low cost  Features for complex logic high speed low power  Easy to use fully supported by Xilinx and third-party software

37. Solutions for Low-Cost,High- Volume Applications  Low cost programmable logic SpartanXL FPGAs available XC9500XL CPLDs available  High performance  System-level features  Ease of evaluation and design WebFITTER, Foundation 1.5i software available