1. XILINX FPGAs Xilinx lunched first commercial FPGA XC2000 in 1985
Xilinx SRAM based family devices are
XC2000
XC3000
XC4000
Spartan
Virtex
Xilinx has recently introduced an antifuse based FPGA is XC8100.
XC3000 and XC4000 has improvements in Density, Performance, Pin count, Voltage levels and Functionality
XC4000 and Spartan have same basic architecture and they differ in density and voltage levels
XC4000 has equivalent gates

2. XC4000 FPGA Architecture

3. XC4000 CLB

4. XC4000 CLB
Each CLB consists LUTs, Multiplexers, Registers, and path for Control signals.
XC3000 had single programmable LUT with 5 inputs
Each LUT has 5-ns delay which is independent of function being implemented
XC4000 consists 3 function generator (F,G, and H) and each based on LUT
Function generators F and G can implement any 4 variable Boolean function
Function generator H can implement any 3 variable function only and it gets the input from F and G LUTs

5. XC4000 CLB
Three LUTs can be programmed to implement a logic function up to 9 variables
Each CLB has 2 edge triggered flip-flops and are programmed to operate as flip-flop or a latch
Flip-flops can get their inputs from LUTs or from Din input
LUTs can drive the outputs X and Y directly and are connected to interconnect network

6. XC4000 Programmable Interconnect Resource

7. Contd.,
XC4000 was designed with interconnect structure is arranged in horizontal and vertical channels
Each channel has 3 types of general purpose interconnect
Single length line or Short lines
Long lines
Double length line or Very Long lines
The short length lines span a single CLB
The long length lines span two CLBs
The very long length lines span the entire width of the chip