4 Programmable logicAn integrated circuit that can be programmed/reprogrammed with a digital logic of a curtain level.Started at late 70s and constantly growingNow available of up to approximately 700K Flip-Flops in a single chip.
5 Advantages Short Development time Reconfigurable Saves board space Flexible to changesNo need for ASIC expensive design and productionFast time to marketBugs can be fixed easilyOf the shelf solutions are available
6 Programmable switch or fuse How it Began : PLAProgrammable Logic ArrayFirst programmable device2-level and-or structureOne time programmableABCAND planeProgrammable switch or fuseOR plane
8 FPGA - Field Programmable Gate Array Programmable logic blocks (Logic Element “LE”) Implement combinatorial and sequential logic. Based on LUT and DFF.Programmable I/O blocks Configurable I/Os for external connections supports various voltages and tri-states.Programmable interconnect Wires to connect inputs , outputs and logic blocks.clocksshort distance local connectionslong distance connections across chipI/OLogic blockInterconnection switches
9 Configuring LUT LUT is a RAM with data width of 1bit. The contents are programmed at power upTruth TableProgrammed LUTabcy1Required Function
10 Special FPGA functions Internal SRAMEmbedded Multipliers and DSP blocksEmbedded logic analyzerEmbedded CPUsHigh speed I/O (~10GHz)DDR/DDRII/DDRIII SDRAM interfacesPLLs
16 Cyclone II Logic ArrayBuild of LABs (logic array blocks) and reconfigurable interconnect
17 Cyclone II Logic Array Block (LAB) LE1LE2LE3LE4LE13LE14LE16LE154Fast Local InterconnectDirect link interconnect to leftDirect link interconnect to right16 LEsLocal InterconnectLE carry chainsRegister chainsLAB Control Signals2 CLK2 CLK ENA2 ACLR1 SCLR1 SLOAD
25 Memory True Dual port RAM/ROM with dual clock Variable data width 4K×1, 2K×2, 1K×4, 512×8, 512×9, 256×16, 256×18128×32, 128×36 (not available in true dual-port mode)Input data and address are registered1 Clock Write latencyOutput data can be registeredRead latency of 1 or 2 clocksByte Enable
27 Cyclone II Multipliers 18x18 or 2 9x9 modesUp to 250MHz Performance18Sign_XXYSign_YInput Registers36ClockClearOutput Registers
28 Delays and maximal frequency Gate delay – Delay of logic elementDFF delay tco (tsu - Very small)Interconnect delay1/Fmax = Tco + Tpdlogic + Tpd interconnectMaximum Frequency is the fastest speed a circuit containing flip-flops can operate.