Presentation is loading. Please wait.

Presentation is loading. Please wait.

Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable.

Published by Modified over 8 years ago

Similar presentations

Presentation on theme: "Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable."— Presentation transcript:

1 Implementing Digital Circuits Lecture L3.1

2 Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

3 Discovery of the Electron -- 1898 J. J. Thomson Cathode Tube Cavendish Labs Electric Field -- “corpuscle”

4 The Vacuum Tube

5 The First Point-Contact Transistor 1947 Bell Labs Museum

6 The First Junction Transistor 1951 Bell Labs Lab model M1752 Outside the Lab

7 Texas Instrument’s First IC -- 1958 Jack Kilby Robert Noyce Fairchild Intel

8 Moore’s Law

9

10 Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

11 Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates to arithmetic logic units Becoming obsolete with the development of programmable logic devices (PLDs)

12 Transistor-Transistor Logic (TTL) Diode-Transistor Logic DTL Transistor-Transistor Logic (TTL) "Totem Pole" output

13 TTL Chips

14 TTL NAND, NOR, XOR

15 TTL Multiple-input Gates

16 Small-Scale Integrated (SSI) Circuits 1 to 10 gates NAND gate has 4 transistors

17 Medium-Scale Integrated (MSI) Circuits 10-100 gates Adders Comparators Multiplexers Decoders

18 Large-Scale Integrated (LSI) Circuits 100-1000 gates Arithmetic Logic Units

19 Very-Large-Scale Integrated (VLSI) Circuits >1000 gates Microprocessors Programmable Logic Devices (PLDs) Complex Programmable Logic Devices (CPLDs) Field Programmable Gate Arrays (FPGAs)

20 Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

21 A Programmable Logic Device

22 A = X & !X & Y & !Y = 0 & 0 = 0

23 A Programmable Logic Device A = X & !X & Y & !Y = 0 & 0 = 0 Z = A # B = 0 # B = B

24 Alternate PLD Representation

25 Make PLD Connections for AND XY X!XY!Y A B Z 1 2 XX XXXX

26 Make PLD Connections for OR XY X!XY!Y A B Z 1 2 X X

27 Make PLD Connections for NAND XY X!XY!Y A B Z 1 2 X X

28 Make PLD Connections for NOR XY X!XY!Y A B Z 1 2 XX XXXX

29 Make PLD Connections for XNOR XY X!XY!Y A B Z 1 2 XX XX A B C 0 0 1 0 1 0 1 0 0 1 1 1

30 Make PLD Connections for XOR XY X!XY!Y A B Z 1 2 XX XX A B C 0 0 0 0 1 1 1 0 1 1 1 0

31 The GAL 16V8 1 2 3 4 5 6 7 9 1011 12 8 19 20 17 18 15 16 13 14 GND Vcc I/CLK II/O I I I I I I I I/OE I/O GAL 16V8

32 Structure of the GAL 16V8 PLD

33 GAL 16V8 Polarity Control OE X A B C X closed B = 0 C = A ­ open B = 1 C = !A Polarity Pin

34 Typical PLD Flip-Flops

35 Structure of the GAL 16V8 PLD

36 XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE 1149.1 JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

37 XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

38 XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O 3672108144216 8001600240032004800 57.5 10 3672108144216 3472108133166 Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ160 288 6400 10 288 192 HQ208 BG352 PQ160 HQ208 BG352 957295108951449521695288

39 PLDT-3 Xilinx XC95108 CPLD 7 segment display Switches LEDs Buttons

40 Xilinx 95108 6 function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

41 Architecture of the Xilinx XC95108 CPLD

42 Each Xilinx 95108 macrocell contains a D flip-flop Controlled inverter

43 Each Xilinx 95108 macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z

44 Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

45

46 Block diagram of Xilinx Spartan-3 FPGA

47 Each Spartan-3 CLB contains four CLB slices

48 Left-hand Slice SLICEM

49 Top of Left-hand Slice SLICEM

50 16 x 1 SRAM Lookup Table

51 Look Up Tables  Capacity is limited by number of inputs, not complexity  Choose to use each function generator as 4 input logic (LUT) or as high speed sync.dual port RAM Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB Example: A B C D Z 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1... 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 1 Look Up Table Combinatorial Logic A B C D Z 4-bit address G Func. Gen. G4 G3 G2 G1 WE 2 (2 ) 4 = 64K !

52 Center of Left-hand Slice SLICEM

53 Bottom of Left-hand Slice SLICEM

54 Xilinx Spartan-3 FPGAs

55 Block RAM

56

57

58

59 Digital Clock Manager (DCM)

60 Delay-Locked Loop (DLL)

61 Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable Logic Devices –PLDs and CPLDs Field Programmable Gate Arrays (FPGAs) –The Xilinx Spartan 3 –The Xilinx Virtex Family

62 Virtex FPGAs For info on Virtex 1000 boards, see http://www.zarx.info/

63 Virtex-II FPGAs

64 Virtex-II Pro FPGAs

65 CPLDs vs. FPGAs

66 Virtex-4 FPGAs

67

Download ppt "Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable."

Similar presentations

PLDs ROM : Programmable OR array

PLDs ROM : Programmable OR array
Lecture 15 Finite State Machine Implementation

Lecture 15 Finite State Machine Implementation
Programmable Logic Devices

Programmable Logic Devices
Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
Survey of Reconfigurable Logic Technologies

Survey of Reconfigurable Logic Technologies
Programmable Logic Devices

Programmable Logic Devices
©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.

©2004 Brooks/Cole FIGURES FOR CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES Click the mouse to move to the next page. Use the ESC key.
PLD Technology Basics. Basic PAL Architecture DQ Q CLK OE Fuse.

PLD Technology Basics. Basic PAL Architecture DQ Q CLK OE Fuse.
Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.1.
A Programmable Logic Device Lecture 4.3. A Programmable Logic Device Multiple-input Gates A 2-Input, 1-Output PLD.

A Programmable Logic Device Lecture 4.3. A Programmable Logic Device Multiple-input Gates A 2-Input, 1-Output PLD.
Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.
The Xilinx 95108 CPLD Lecture 4.2. XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s.

The Xilinx CPLD Lecture 4.2. XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s.
The GAL16V8 PLD Module M2.1 Chapter 4. Basic PLD Structure.

The GAL16V8 PLD Module M2.1 Chapter 4. Basic PLD Structure.
Transistor-Transistor Logic (TTL) Lecture L4.1. Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates.

Transistor-Transistor Logic (TTL) Lecture L4.1. Transistor-Transistor Logic (TTL) Developed in mid-1960s Large family (74xx) of chips from basic gates.
Programmable Logic Devices by Abdulqadir Alaqeeli 1/27/98.

Programmable Logic Devices by Abdulqadir Alaqeeli 1/27/98.
Introduction to Computer Engineering by Richard E. Haskell Xilinx CPLDs Lab 2b Module M2.4.

Introduction to Computer Engineering by Richard E. Haskell Xilinx CPLDs Lab 2b Module M2.4.
FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.
Silicon Programming--Altera Tools1 “Silicon Programming“ programmable logic Altera devices and the Altera tools major tasks in the silicon programming.

Silicon Programming--Altera Tools1 “Silicon Programming“ programmable logic Altera devices and the Altera tools major tasks in the silicon programming.
FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.

FPGAs and VHDL Lecture L13.1 Sections 13.1 – 13.3.
Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.

Introduction to Field Programmable Gate Arrays (FPGAs) COE 203 Digital Logic Laboratory Dr. Aiman El-Maleh College of Computer Sciences and Engineering.

Similar presentations

Ads by Google