Presentation is loading. Please wait.

Presentation is loading. Please wait.

® Spartan-II High Volume Solutions Overview. ® www.xilinx.com High Performance System Features Software and Cores Smallest Die Size Lowest Possible Cost.

Published byAustin Curtis Modified over 8 years ago

Similar presentations

Presentation on theme: "® Spartan-II High Volume Solutions Overview. ® www.xilinx.com High Performance System Features Software and Cores Smallest Die Size Lowest Possible Cost."— Presentation transcript:

1 ® Spartan-II High Volume Solutions Overview

2 ® www.xilinx.com High Performance System Features Software and Cores Smallest Die Size Lowest Possible Cost Low Cost Plastic Packages Streamlined Testing Xilinx Spartan Series FPGAs

3 ® www.xilinx.com 100,000 gates for $10 Pricing for 250,000 units, end-2000, slowest speed, cheapest package Spartan-II Expands the Spartan Series  Expands ASIC market coverage over Spartan-XL —2-3X gates per I/O pin, 5X total gates —2X gates per dollar —2X I/O performance  Integrates more system functions —DLLs, FIFOs, translators, bus interfaces (PCI)  Fast, predictable routing performance and easy-to- use design flows

4 ® www.xilinx.com 40K $10 Spartan-XL Spartan-II System Gates 1998 1999 2000 2001 Spartan-III 30K 250K 100K FIFOs PALs HDLC UARTs 32-bit, 33- MHz PCI PCI-MIPS Bridge 64 Bit PCI Reed Solomon Encoder ATM IMA Graphics Card Office Networking Set-Top Box Embedded uP Apps Video Line Buffer Cable Modem Ethernet MAC Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe Higher Density Enables New Applications

5 ® www.xilinx.com 50 100 150 200 250 200K 175K 150K 125K 100K 75K 50K 25K 0 I/Os System Gates XCS30/XL XCS20/XL XCS05/XL XCS40/XL ASICs & Spartan FPGAs Gates vs. I/Os XCS10/XL Spartan-II FPGAs Gate Arrays Spartan/XL XC2S15 XC2S30 XC2S50 XC2S100 XC2S150 XC2S200

6 ® www.xilinx.com Reprogrammability is the Advantage Advantages over ASICs  Time to Market advantage —First to market increases revenue yield  Time in Market advantage —Increases the revenue yield while in field

7 ® www.xilinx.com Spartan-II  Low Cost  Low Power  Density (15K to 200K)  High VolumeSpartan-II  Low Cost  Low Power  Density (15K to 200K)  High Volume Virtex-E  High I/O  Performance  Density (50K to 3.2M)  System integration Virtex-E  High I/O  Performance  Density (50K to 3.2M)  System integration Architecture FPGA Focus Products CY00

8 ® www.xilinx.com Spartan-II Product Matrix

9 ® www.xilinx.com -5 Spartan-XL Spartan-II -4 Speed Virtex -6 -5 -6 -4 Spartan-II Speed Grades  Strategy —Fast enough for high volume applications —Simplify speed grade offering  Implementation —Spartan-II offers -5 & -6

10 ® www.xilinx.com DLL CL IOB IOBIOB IOBIOB IOBIOB IOBIOB DLL CL... CLB RAMRAM RAMRAM RAMRAM RAMRAM I/O Routing Ring True Dual-Port TM 4K bit RAM Clock management Multiply clock Divide clock De-skew clock Chip to Backplane PCI 33MHz 3.3V PCI 33MHz 5.0V PCI 66MHz 3.3V GTL, GTL+, AGP Chip to Memory HSTL-I, HSTL-III HSTL-IV SSTL3-I, SSTL3-II SSTL2-I, SSTL2-II CTT Chip to Chip LVTTL, LVCMOS SelectI/O TM Technology Logic and Distributed RAM Configurable Logic Block (CLB) Delay Locked Loop (DLL) 4Kx1 2Kx2 1Kx4 512x8 256x16 Block Memory Spartan-II Architecture

11 ® www.xilinx.com 2ns CLB Array High Performance Routing  Routing delay depends primarily on distance —Direction independent —Device-size independent  Predictable for early design analysis  Critical for cores

12 ® www.xilinx.com $10 1998 1999 2000 Spartan-XL Spartan-II Graphics Add-In Card Office Networking Set-Top Box xDSL Modems 200 MHz Memory Continuum - Transparent Bandwidth Cable Modems Internet Devices DSP Coefficients Small FIFOs 16x1 Distributed RAM Large FIFOs Video Line Buffers Cache Tag Memory 4Kx1 2Kx2 1Kx4 512x8 256x16 Block RAM SDRAM SGRAM PB SRAM DDR SRAM ZBT SRAM QDR SRAM External RAM Pricing for 250,000 units, slowest speed, cheapest package, indicated timeframe Block RAM Enables New Applications

13 ® www.xilinx.com RAMB4_S4_S16 WEB ENB RSTB CLKB ADDRB[7:0] DIB[15:0] WEA ENA RSTA CLKA ADDRA[9:0] DIA[3:0] DOA[3:0] DOB[15:0] Spartan-II True Dual-Port Block RAM Port A Port B W R W R W R R W Data Flow Spartan-II A to B Yes B to A Yes A to A Yes B to B Yes Spartan-II Block RAM  True dual-port static RAM - 4K bits —Independently configurable port data width –4K x 1; 2K x 2; 1K x 4; 512 x 8; 256 x 16 —Fast synchronous read and write –2.5ns clock-to-output with 1.0ns input address/data setup

14 ® www.xilinx.com DLL1 DLL2 DLL3 DLL4 Deskew clocks on chip Manage up to 4 system clocks Deskew clocks on board Cascade DLLs Generate clocks multiply divide shift Convert clock levels using SelectI/O Delay Locked Loops lower memory and board costs Spartan-II Clock Management

15 ® www.xilinx.com Spartan-II SelectI/O 3 Types of I/O Interfaces SDRAM SSTL GTL+ LVTTL LVCMOS HSTL SRAM PCI Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI33-5V, PCI33-3.3V, GTL, GTL+, AGP Chip to Chip LVTTL, LVCMOS, 5-volt tolerant

16 ® www.xilinx.com I/O Standards Summary

17 ® www.xilinx.com I/O Performance Using SelectI/O & DLL Technology

18 ® www.xilinx.com Spartan-II Core Support  BaseBLOX basic functions —Arithmetic (adders, counters, multipliers, etcetera) —Memory (single port, dual port, FIFO, etcetera)  AllianceCORE support —Microprocessor peripherals —Microcontrollers —Memory controllers (SDRAM) —Communications –ATM, Ethernet, error correction (Reed-Solomon, Viterbi), telecom (HDLC), etc.

19 ® www.xilinx.com Spartan-II PCI LogiCORE Solutions  PCI32/33 —XC2S30/50/100/150-5 PQ208 –Pre-release version based on advance speed files  PCI64/33 —XC2S100/150-6 FG456  New PCI back-end design - in development —PLX-like, including DMA, FIFOs, and interrupt control  PCI-X Support - under evaluation

20 ® www.xilinx.com GTL+ 5-volt tolerant I/O SDRAM QDR SRAMs MIPS uP 2x CLK PCI PLL $7.50 PCI Master/ Target Controller $15 SSTL-3 Translators $4 FIFOs Dual Ports $7$2 $40 $6 GTL+ Backplane Drivers HSTL Translators $6 Spartan-II: System Integration PCI-MIPS System Controller SSTL3 Clock Mgmt - Board deskew Memory

21 ® www.xilinx.com DLLs Delay Locked Loops SelectI/O Technology Memory Distributed + Block External 100,000 Gates for $10 Reprogrammable ASIC Replacement! Pricing for 250,000 units, end-2000, slowest speed, cheapest package Spartan-II: The Total Solution

22 ® www.xilinx.com Reprogrammability at ASIC prices Spartan-II Summary  Expand ASIC market coverage for Spartan Series —More gates per I/O and more gates per dollar —Higher density and performance —New features: Block RAM, DLL, SelectI/O technology  Optimized for low cost  Software support in 2.1i with latest service pack

Download ppt "® Spartan-II High Volume Solutions Overview. ® www.xilinx.com High Performance System Features Software and Cores Smallest Die Size Lowest Possible Cost."

Similar presentations

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.
Spartan-II Reed-Solomon Solutions for Under $10 Xilinx at Work in Hot New Technologies February 2000 ®

Spartan-II Reed-Solomon Solutions for Under $10 Xilinx at Work in Hot New Technologies February 2000 ®
® Xilinx FPGA Architecture Overview. ® www.xilinx.com Virtex/Spartan-II Top-level Architecture  Gate-array like architecture  Configurable logic blocks.

® Xilinx FPGA Architecture Overview. ® Virtex/Spartan-II Top-level Architecture  Gate-array like architecture  Configurable logic blocks.
Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.
FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.
George Mason University ECE 645 – Computer Arithmetic Introduction to FPGA Devices.

George Mason University ECE 645 – Computer Arithmetic Introduction to FPGA Devices.
The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.

The Spartan 3e FPGA. CS/EE 3710 The Spartan 3e FPGA  What’s inside the chip? How does it implement random logic? What other features can you use?  What.
Configurable System-on-Chip: Xilinx EDK

Configurable System-on-Chip: Xilinx EDK
Programmable logic and FPGA

Programmable logic and FPGA
Features of Modern FPGAs

Features of Modern FPGAs
Introduction to FPGA and DSPs Joe College, Chris Doyle, Ann Marie Rynning.

Introduction to FPGA and DSPs Joe College, Chris Doyle, Ann Marie Rynning.
Using Programmable Logic to Accelerate DSP Functions 1 Using Programmable Logic to Accelerate DSP Functions “An Overview“ Greg Goslin Digital Signal Processing.

Using Programmable Logic to Accelerate DSP Functions 1 Using Programmable Logic to Accelerate DSP Functions “An Overview“ Greg Goslin Digital Signal Processing.
The Xilinx Spartan 3 FPGA EGRE 631 2/2/09. Basic types of FPGA’s One time programmable Reprogrammable (non-volatile) –Retains program when powered down.

The Xilinx Spartan 3 FPGA EGRE 631 2/2/09. Basic types of FPGA’s One time programmable Reprogrammable (non-volatile) –Retains program when powered down.
Hardware Overview Net+ARM – Well Suited for Embedded Ethernet

Hardware Overview Net+ARM – Well Suited for Embedded Ethernet
® ChipScope ILA TM Xilinx and Agilent Technologies.

® ChipScope ILA TM Xilinx and Agilent Technologies.
Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January 2000 +

Xilinx at Work in Hot New Technologies ® Spartan-II 64- and 32-bit PCI Solutions Below ASSP Prices January
Agenda Last Year’s Mission The Road Ahead Summary.

Agenda Last Year’s Mission The Road Ahead Summary.
CoolRunner ™ -II Low Cost Solutions. Quick Start Training Introduction CoolRunner-II system level solution savings Discrete devices vs. CoolRunner-II.

CoolRunner ™ -II Low Cost Solutions. Quick Start Training Introduction CoolRunner-II system level solution savings Discrete devices vs. CoolRunner-II.
Xilinx Spartan Series High Performance, Low Cost FPGAs with on-chip SelectRAM Memory.

Xilinx Spartan Series High Performance, Low Cost FPGAs with on-chip SelectRAM Memory.
Programmable Solutions in Video Capture/Editing. Overview  Xilinx - Industry Leader in FPGAs/CPLDs High-density, high-speed, programmable, low cost logic.

Programmable Solutions in Video Capture/Editing. Overview  Xilinx - Industry Leader in FPGAs/CPLDs High-density, high-speed, programmable, low cost logic.

Similar presentations

Ads by Google