Day 29: November 10, 2014 Memory Core: Part 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 29: November 10, 2014 Memory Core: Part 1 Penn ESE370 Fall2014 -- DeHon
Today 5T/6T SRAM DRAM Writing Charge sharing Precharge Penn ESE370 Fall2014 -- DeHon
Memory Bank Penn ESE370 Fall2014 -- DeHon
5T SRAM Memory Bit Penn ESE370 Fall2014 -- DeHon
Write (preclass 1) Assuming properly select only one WL, what does write circuit look like? What transistors are ON when writing a 0 over a cell that holds a 1? Drive with inverter at BL Width Wwrite Voltage written? 1V Penn ESE370 Fall2014 -- DeHon
Write (preclass 1) Assuming properly select only one WL, what does write circuit look like? Voltage written? 1V Penn ESE370 Fall2014 -- DeHon
Write Conclude? Writing into cell is a ratioed operation. Penn ESE370 Fall2014 -- DeHon
Write (preclass 2) Assuming properly select only one WL, what does write circuit look like? How different when writing a 1 over a cell holding a 0 ? 1V Penn ESE370 Fall2014 -- DeHon
6T Cell How does 6T make it easier to perform writes? Penn ESE370 Fall2012 -- DeHon
Preclass 3 Initially Close switch Voltage at A? A @ 1V B @ 0V Penn ESE370 Fall2014 -- DeHon
Preclass 3 Initially QA=1V*C1=C1 Close switch Qtot=Vfinal*(C1+C0) B @ 0V QA=1V*C1=C1 Close switch Qtot=Vfinal*(C1+C0) Charge conservation QA=Qtot C1=Vfinal*(C1+C0) Penn ESE370 Fall2014 -- DeHon
Consider (preclass 4) Read: What happens to voltage at A when WL turns from 01? Assume Waccess large Waccess >> Wpu=1 BL initially 0 A initially 1 Penn ESE370 Fall2014 -- DeHon
Voltage After enable Word Line QBL = 0 QA = (1V)(g(2+Waccess)C0) CBL>>CA=(g(2+Waccess)C0) After enable Waccess (Waccess large) Total charge QBL +QA roughly unchanged Distributed over larger capacitance~=CBL VA=VBL~= CA/CBL Penn ESE370 Fall2014 -- DeHon
Larger Resistance? What happens if Waccess small? Waccess < Wpu Penn ESE370 Fall2014 -- DeHon
Larger Resistance? What happens if Waccess small? Waccess < Wpu Takes time to move charge from A to BL Moves more slowly than replished by pu Penn ESE370 Fall2014 -- DeHon
Simulation: Waccess=100 Penn ESE370 Fall2014 -- DeHon
Simulation Penn ESE370 Fall2014 -- DeHon
Charge Sharing Conclude: charge sharing can pull down voltage Penn ESE370 Fall2014 -- DeHon
Consider What happens to voltage at A when WL turns from 01? Assume Waccess large Penn ESE370 Fall2014 -- DeHon
Simulation Waccess=20 Penn ESE370 Fall2014 -- DeHon
Simulation Waccess=4 Penn ESE370 Fall2014 -- DeHon
Charge Sharing Conclude: charge sharing can lead to read upset Charge redistribution adequate to flip state of bit Penn ESE370 Fall2014 -- DeHon
How might we avoid? Penn ESE370 Fall2014 -- DeHon
Charge to middle Voltage Charge bitlines to Vdd/2 before begin read operation Now charge sharing doesn’t swing to opposite side of midpoint Penn ESE370 Fall2014 -- DeHon
Pre-Charge Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE370 Fall2014 -- DeHon
Simulation Waccess=20 Penn ESE370 Fall2014 -- DeHon
Compare Both Waccess=20; vary precharge Penn ESE370 Fall2014 -- DeHon
Simulation Waccess=20 (precharge Vdd/2, reading 0) Penn ESE370 Fall2014 -- DeHon
Simulation Waccess=20 (with precharge Vdd/2) Penn ESE370 Fall2014 -- DeHon
Pre-Charge Use one phase of clock to charge a node to some initial value before operation Precharge Transistor Can be large Penn ESE370 Fall2014 -- DeHon
5T/6T SRAM Questions? Penn ESE370 Fall2014 -- DeHon
Idea Memory can be compact Demands careful sizing Penn ESE370 Fall2014 -- DeHon
Admin HW7 due tomorrow Project 2 out Due 2 weeks from tomorrow Tuesday before Thanksgiving Penn ESE370 Fall2014 -- DeHon