1. Day 20: October 17, 2014 Ratioed Logic
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 20: October 17, 2014
Ratioed Logic
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2. Previously Restoration and Noise Margins CMOS Gates Drive rail-to-rail
Only one transistor turned on in steady state
Only subthreshold current in steady state
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3. Today Ratioed Gates Break all the rules… (nice properties) Correctness
Not rail-to-rail, steady-state-current…
Correctness
Performance
Power
Implications
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4. Note on what about to see
Not clear win
Should be able to analyze
Chance to exercise analysis
Kind of thing you want to be able to analyze
Pattern should recognize
Stepping stone to more interesting things to come…
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5. Idea Building both pull-up and pull-down can be expensive – many gates
Seems wasteful to build logic function twice
Once in pullup, once in pulldown
Large capacitance
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6. Idea Maybe only need to build one Build NFET pulldown
Exploit high N mobility
traditional
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7. Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ?
WP=1
WN=1
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8. Ratioed Inverter Does this work? Vout for Vin=0V ? Vout for Vin=1V ?
WP=1
WN=1
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9. Ratioed Inverter Wn=1
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10. Ratioed Equations PMOS roughly fixed current (resistance)
VGS pinned at –Vdd
NMOS current dependent on Vin
Voltage controlled resistance
mn=2mp
Wp=Wn=1
Rp=?
Rp=Rp0=2R0
Vin=Vdd=?
Vin=Vdd/2=?
Only at Vin=Vdd
Does Rn=Rn0=R0
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11. Ratioed Inverter How do we need to size N to make it work? WP=1
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12. DC Transfer Function
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13. Ratioed Inverter How do we need to size P to make it work? WN=1
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14. P vs. N Conclude: still prefer N to P for ratioed logic
….at least for now
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15. Worst-Case Output Drive Strength?
Rdrive?
WP=1
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16. Noise Margin Tradeoff
What is impact of increasing (reducing) noise margin?
On size
On input capacitance
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17. Ratioed Inverter Sizing
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18. Ratioed Inverter Sizing
What causes knee in curve at high end?
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19. S D
Non-VSAT Equations
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20. Non-VSAT Equations P looks roughly like current sourceD
Non-VSAT Equations
P looks roughly like current source
Must Match current with N
Determine Vds
How does Wn effect Vds?
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21. Non-VSAT Equations Once drop into linear region Isdp constant = Idsn
Vds < Vgs-Vt
Constant = (Vgs-Vt) Vds
Vds α 1/ (Vgs-Vt)
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22. Size for R0/2 drive? How do we size for R0/2 drive?
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23. Compare Static CMOS For Rdrive=R0/2 inverter Total Transistor Width?
Input capacitance load?
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24. Power? Istatic ? Output high? Output low? Ileak Ipmos_on
Vdd/(R0/2) -- for our sample case
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25. Power Ptot ≈ a(½Cload+Csc)V2f +PlowV2/Rpon
+(1-Plow)VI’s(W/L)e-Vt/(nkT/q)
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26. How size for R0/2 drive?
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27. How size for R0/2 drive?
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28. How size for R0/2 drive? How size K-input nor?
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29. When better than CMOS nor-k?
Better = smaller, lower input capacitance
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30. Which Implementation is faster in ratioed logic?
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31. Illustrates
Preferred gate changes
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32. Ideas There are other logic disciplines We have the tools to analyze
Ratioed Logic
Tradeoff noise margin for
Reduced area? Capacitive load?
Dissipates static power in one mode
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33. Admin Project Should have read it
Build and simulated baseline over weekend
Start list of optimizations to try
If don’t have list talk with Ron or André during office hours
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