1. Day 21: October 21, 2013 Design Space Exploration
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 21: October 21, 2013
Design Space Exploration
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2. Today Example to discuss and illustrate design space
You will want to be exploring design space for Project 1
Chance to talk about trends
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3. Design Problem Identify equivalence of two 32b inputs
Minimize Total Energy
Assume match case uncommon
Most of the time, it won’t be matched
Deliberately focus on Energy to complement project
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4. Idea: Design Space Explore
Identify options
All the knobs you can turn
Explore space systematically
Formulate continuum where possible
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5. Problem Solvable First, make sure we have a solution
…so we know our main goal is optimization
What look like built out of nand2 gates?
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6. Total Power Ptot ≈ a(½Cload+Csc)V2f+VI’s(W/L)e-Vt/(nkT/q)
+PlowV2/Rpon
+(1-Plow)VI’s(W/L)e-Vt/(nkT/q)
What can we do to reduce power?
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7. Knobs What are the options and knobs we can turn?
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8. Design Space Dimensions
Vdd
Topology
Gate choice, logical optimization
Fanin, fanout, Serial vs. parallel
Sizing
Gate style / logic family
CMOS, Ratioed (N load, P load)
Vth
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9. S D
Equations
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10. Reduce Vdd What happens as reduce V? Energy? Switching Delay? Dynamic
Static
Switching Delay?
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11. Old Reduce V (no vsat) tgd=Q/I=(CV)/I tgd impact? tgd α 1/V
Id=(mCOX/2)(W/L)(Vgs-VTH)2
tgd impact?
tgd α 1/V
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12. Reduce V (velocity saturation)
tgd=Q/I=(CV)/I
Ids=(nsatCOX)(W)(Vgs-VTH-VDSAT/2)
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13. How Reduce Short-Circuit Power?
Psc = aCscV2 f
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14. Vdd
How low can we push Vdd?
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15. Gate What gates might we build? High fanin? Serial-Parallel?
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16. Sizing
How do we want to size gates?
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17. Logic Family Considerations for each logic family? CMOS
Ratioed with PMOS load
Ratioed with NMOS load
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18. Increase Vth? What is impact of increasing threshold on
Dynamic Energy?
Leakage Energy?
Delay?
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19. Increase Vth tgd=Q/I=(CV)/I Ids=(nsatCOX)(W)(Vgs-VTH-VDSAT/2)
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20. Ideas We know many things can do to our circuits Design space is large
Systematically identify dimensions
Identify continuum tuning when possible
Watch tradeoffs
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21. Admin Project Should have simulated baseline
List of optimizations to try
If don’t have list talk with Spencer or André during office hours
Milestone is a bare minimum
Really should be into exploring options this week
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