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Day 16: October 7, 2013 Inverter Performance

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Presentation on theme: "Day 16: October 7, 2013 Inverter Performance"— Presentation transcript:

1 Day 16: October 7, 2013 Inverter Performance
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 16: October 7, 2013 Inverter Performance Penn ESE370 Fall DeHon

2 Previously Delay as RC-charging Transistor Capacitance Drive Current
As a function of geometry (W/L) Penn ESE370 Fall DeHon

3 Today t-model Sizing Large Fanout Capacitance Revisited Miller Effect
Parallel Gate Capacitance Penn ESE370 Fall DeHon

4 Transistor Sizing What happens to Ids as a function of W?
What happens to Cg as a function of W? Conclude: faster transistors present more load on their inputs Penn ESE370 Fall DeHon

5 First Order Delay R0 = Resistance of minimum size NMOS device
C0 = gate capacitance of minimum size NMOS device Rdrive = R0/W Cg = WC0 Penn ESE370 Fall DeHon

6 First Order Delay (alt view)
I0 = Ids of minimum size NMOS device C0 = gate capacitance of minimum size NMOS device Idrive = WI0 Cg = WC0 Penn ESE370 Fall DeHon

7 t model All delays are RC delays (CV/I delays)
Always have an R0C0 term (C/I term) t = R0C0 (equivalently C0/I0) Express all delays in t units Like l units for measurement Separate delay into Technology dependent term t = R0C0 Technology independent term Penn ESE370 Fall DeHon

8 Inverter Sizing What is the impact of the delay on the middle inverter if double size of all the transistors? Penn ESE370 Fall DeHon

9 How Size How size to equalize Rise and Fall?
mn=500cm2/Vs, mp=200cm2/Vs When velocity saturated Rdrive=R0/2 (Idrive=2I0) Penn ESE370 Fall DeHon

10 SPICE Simulation Penn ESE370 Fall DeHon

11 SPICE Simulation 22nm Penn ESE370 Fall DeHon

12 Worst Case Delay Largest R Rdrive = max(Rpullup,Rpulldown)
If equalize Rpullup and Rpulldown Rdrive = Rpullup=Rpulldown Penn ESE370 Fall DeHon

13 Equalizing Delay For simplicity, for today Assume Wp=Wn equalizes Ids
Penn ESE370 Fall DeHon

14 Large Fanout What is delay if must drive fanout=100?
Penn ESE370 Fall DeHon

15 What Delay? What is delay here? Penn ESE370 Fall DeHon

16 How Size How size transistors to minimize delay?
Penn ESE370 Fall DeHon

17 Optimizing Delay = 2Wmid/1 + 200/Wmid How minimize?
D(Delay)/D(Wmid) = 0 2 – 200/(Wmid)2=0 Wmid=sqrt(100) = 10 Penn ESE370 Fall DeHon

18 Delay? Delay at optimal Wmid? Penn ESE370 Fall DeHon

19 Try again What is the delay here? Penn ESE370 Fall DeHon

20 …and Again Delay here? Penn ESE370 Fall DeHon

21 Lesson Don’t drive large fanout with a single stage
Must scale up over a number of stages …but not too many Exact number will be technology dependent Penn ESE370 Fall DeHon

22 Charge on Capacitors Penn ESE370 Fall DeHon

23 Questions What is DQ when switched? Equivalent Capacitance?
Contribution from each transistor? Penn ESE370 Fall DeHon

24 Gate-Drain Capacitance
What is the voltage across Vin—V2 When Vin=Vdd When Vin=Gnd What is DV across Vin—V2 when Vin switches from Vdd to Gnd? Penn ESE370 Fall DeHon

25 Miller Effect For an inverting gate
Capacitance between input and output must swing 2 Vhigh Or…acts as double-sized capacitor Penn ESE370 Fall DeHon

26 If Time Permits (back to scaling) Penn ESE370 Fall DeHon

27 Improving Gate Delay tgd=Q/I=(CV)/I V S×V Id  S×Id C  S×C
How might we accelerate? tgd=Q/I=(CV)/I V S×V Id=(mCOX/2)(W/L)(Vgs-VTH)2 Id  S×Id C  S×C tgd  S×tgd Don’t scale V: VV II/S tgd  S2×tgd Lower C. Don’t scale V. Penn ESE370 Fall DeHon

28 …But Power Dissipation (Dynamic)
Capacitive (Dis)charging P=(1/2)CV2f V V C  S×C Increase Frequency? f  f/S2 ? P  P/S If not scale V, power dissipation not scale down. Penn ESE370 Fall DeHon

29 …And Power Density P P/S (increase frequency) But… A  S2×A
What happens to power density? P/A  (1/S3)P Power Density Increases …this is where some companies have gotten into trouble… Penn ESE370 Fall DeHon

30 Historical Voltage Scaling
Frequency impact? Power Density impact? Penn ESE370 Fall DeHon

31 Scale V separately from S
tgd=Q/I=(CV)/I V Id=(mCOX/2)(W/L)(Vgs-VTH)2 Id  V2/S×Id C  S×C tgd  (SV/(V2/S))×tgd tgd  (S2/V)×tgd Ideal scale: S=1/100 V=1/100 t=1/100 Fideal=100 Cheating: S=1/100 V=1/10 t=1/1000 Fcheat=1000 fcheat/fideal=10 Penn ESE370 Fall DeHon

32 Power Density Impact P=1/2CV2 f P~= S V2 (V/S2) = V3/S
P/A = (V3/S) / S2 = V3/S3 V=1/10 S=1/100 P/A  1000 (P/A) Penn ESE370 Fall DeHon

33 uProc Clock Frequency MHz
The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE370 Fall DeHon

34 uP Power Density Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 Penn ESE370 Fall DeHon

35 Ideas First order delay reason in t=R0C0 units
Equivalently (C0/I0) units Scaling everything up doesn’t help Drive large capacitive loads in stages Penn ESE370 Fall DeHon

36 Admin HW5 due Tuesday Midterm solutions posted
Penn ESE370 Fall DeHon

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