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Day 2: September 10, 2010 Transistor Introduction

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Presentation on theme: "Day 2: September 10, 2010 Transistor Introduction"— Presentation transcript:

1 Day 2: September 10, 2010 Transistor Introduction
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 10, 2010 Transistor Introduction Penn ESE370 Fall DeHon

2 Today MOSFET Capacitive and resistive loads Simplified models
Zero-th order model Good enough for ??? First order model There are always Rs and Cs Penn ESE370 Fall DeHon

3 MOSFET Metal Oxide Semiconductor Field Effect Transistor New device
Primary active component for the term Three terminal device Voltage at gate controls conduction between two other terminals (source, drain) Penn ESE370 Fall DeHon

4 MOSFET I vs. Vgs, Vds Penn ESE370 Fall DeHon

5 MOSFET I vs. Vgs, Vds Will dig into understanding during term
Today simple ways to reason about gross behavior Static/DC Penn ESE370 Fall DeHon

6 Preclass What voltage do the cases converge to?
Penn ESE370 Fall DeHon

7 Penn ESE370 Fall DeHon

8 Penn ESE370 Fall DeHon

9 Penn ESE370 Fall DeHon

10 Penn ESE370 Fall DeHon

11 Penn ESE370 Fall DeHon

12 Penn ESE370 Fall DeHon

13 Penn ESE370 Fall DeHon

14 Conclude? DC/Steady-State Ignore the capacitors
Penn ESE370 Fall DeHon

15 Quasistatic Static – inputs (and circuit) unchanging, how does it settle? Dynamic – what happens when things change Quasi-Static – inputs transition, circuit responds, and settles Dynamic transition to roughly static states Penn ESE370 Fall DeHon

16 Quasistatic Relevance?
How relevant to a combinational digital circuit? How relevant to a clocked digital circuit? Penn ESE370 Fall DeHon

17 Zero-th Order MOSFET Ideal Switch Vgs > Vth  conducts
Vgs < Vth  does not conduct Vth – threshold voltage Penn ESE370 Fall DeHon

18 Zero-th Order MOSFET Penn ESE370 Fall DeHon

19 N-Type, P-Type N – negative carriers Switch turned on positive Vgs
electrons Switch turned on positive Vgs P – positive carriers holes Switch turned on negative Vgs Vth<0 Vgs<Vth to to conduct Penn ESE370 Fall DeHon

20 Why useful? Penn ESE370 Fall DeHon

21 What happens when Vin=Vdd>Vth
Penn ESE370 Fall DeHon

22 What happens when Vin=Vdd>Vth
Vgs=Vdd > Vth Penn ESE370 Fall DeHon

23 What happens when Vin=Vdd>Vth
Vgs=Vdd > Vth Penn ESE370 Fall DeHon

24 What happens when Vin=Vdd>Vth
Vgs=0 > Vth Vgs=Vdd > Vth Penn ESE370 Fall DeHon

25 What happens when Vin=Vdd>Vth
Vgs=0 > Vth Vgs=Vdd > Vth Penn ESE370 Fall DeHon

26 What happens when Vin=Vdd>Vth
Vgs=0 > Vth V2=Gnd Vgs=Vdd > Vth Penn ESE370 Fall DeHon

27 What happens when Vin=Vdd>Vth
Vgs=0 > Vth V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall DeHon

28 What happens when Vin=Vdd>Vth
Vgs=-Vdd < Vth Vgs=0 > Vth V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall DeHon

29 What happens when Vin=Vdd>Vth
Vgs=-Vdd < Vth Vgs=0 > Vth Vout=Vdd V2=Gnd Vgs=0 < Vth Vgs=Vdd > Vth Penn ESE370 Fall DeHon

30 What happens when Vin=0<Vth
Penn ESE370 Fall DeHon

31 What happens when Vin=0<Vth
V2=Vdd Vout=0 Penn ESE370 Fall DeHon

32 What function? Buffer Vin=Vdd  Vout=Vdd Vin=0  Vout=0
Penn ESE370 Fall DeHon

33 Why Useful? Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits Penn ESE370 Fall DeHon

34 Why adequate? Static analysis – can ignore capacitors
Capacitive loads – resistances don’t matter Feed forward for gates – don’t generally have loops can work forward from known values Logic drive rail-to-rail Don’t have to reason about intermediate voltage levels Penn ESE370 Fall DeHon

35 What not tell us? Delay Dynamics Behavior if not Capacitively loaded
Loops Penn ESE370 Fall DeHon

36 First Order Model Switch Loads input capacitively
Has finite drive strength Penn ESE370 Fall DeHon

37 First Order Model Penn ESE370 Fall DeHon

38 First Order Model Penn ESE370 Fall DeHon

39 Refine to First Order Penn ESE370 Fall DeHon

40 Zero-th Order Tells us how switches set (Vin=0)
V2=Vdd Vout=0 Penn ESE370 Fall DeHon

41 Zero-th Order Tells us how switches set (Vin=0)
V2=Vdd Vout=0 Penn ESE370 Fall DeHon

42 Zero-th Order Tells us how switches set (Vin=0)
Leaves an RC Circuit we can analyze Penn ESE370 Fall DeHon

43 Zero-th Order Tells us how switches set (Vin=0)
Look at middle stage Penn ESE370 Fall DeHon

44 What more this tell us? Delay Quastistatic behavior
Voltage settling with resistive loads At least some basis for reasoning Penn ESE370 Fall DeHon

45 What is this leaving out?
Penn ESE370 Fall DeHon

46 What is this leaving out?
Penn ESE370 Fall DeHon

47 What leaving out? What happens at intermediate voltages
Not rail-to-rail Details of dynamics, including… Input not transition as step Intermediate drive strengths change with Vgs As output charges Vds changes, changing drive strenght Isn’t really 0 current below threshold Penn ESE370 Fall DeHon

48 Engineering Control Vth – process engineer
Drive strength – circuit engineer control with sizing Supply voltages – range set by process, detail use by circuit design Penn ESE370 Fall DeHon

49 Engineering Control: Threshold
Penn ESE370 Fall DeHon

50 Engineering Control: Drive Strength
Penn ESE370 Fall DeHon

51 Wire Capacitance Penn ESE370 Fall DeHon

52 Wire Capacitance Penn ESE370 Fall DeHon

53 Wire Resistance Penn ESE370 Fall DeHon

54 Wire Resistance Penn ESE370 Fall DeHon

55 Wire Resistance Sanity check Wire twice as long = resistors in series
Wire twice as wide = resistors in parallel Penn ESE370 Fall DeHon

56 There are always Rs and Cs
Modeling vs. discrete components Dominant effects Rbig + Rsmall ≈ Rbig Cbig || Csmall ≈ Csmall Penn ESE370 Fall DeHon

57 Admin TA: Andrew Townley Lecture Monday: building gates
atownley seas Office Hours: Lecture Monday: building gates Reading Lab on Wednesday Penn ESE370 Fall DeHon

58 MOSFET Penn ESE370 Fall DeHon

59 Big Ideas MOSFET Transistor as switch
Purpose-driven simplified modeling Aid reasoning Sanity check Simplify design New perspective on Rs and Cs Penn ESE370 Fall DeHon

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