1. Penn ESE370 Fall2014 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 10, 2014 Restoration

2. Today How do we make sure logic is robust –Can assemble into any (feed forward) graph –Can tolerate voltage drops and noise –….while maintaining digital abstraction Penn ESE370 Fall2014 -- DeHon 2

3. Outline Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear Penn ESE370 Fall2014 -- DeHon 3

4. Two Problems 1.Output not go to rail –Stops short of Vdd or Gnd 2.Signals may be perturbed by noise V x = V ideal ± V noise Penn ESE370 Fall2014 -- DeHon 4

5. Wire Resistance Penn ESE370 Fall2014 -- DeHon 5 Monday: R wire =10Ω

6. Wire Resistance 1000  m long wire? 1 cm long wire? Length of integrated circuit chip side? –(we often call an IC chip a “die”) Penn ESE370 Fall2014 -- DeHon 6

7. Die Sizes ChipTrans.YearMakerfeaturemm 2 Bulldozer1.2B2012AMD32nm315 Core i71.4B2012Intel22nm160 GK10 Kepler 7B2012NVIDIA28nm561 Penn ESE370 Fall2014 -- DeHon 7 source: http://en.wikipedia.org/wiki/Transistor_count

8. Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2014 -- DeHon 8

9. Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2014 -- DeHon 9 Rwire Rrest_of_chip

10. IR-Drop Since interconnect is resistive and gates pull current off the supply interconnect –The Vdd seen by a gate is lower than the supply Voltage by V drop =I supply x R distribute –Two gates in different locations See different R distribute Therefore, see different V drop Penn ESE370 Fall2014 -- DeHon 10 R rest_of_chip

11. Output not go to Rail Due to IR drop, “rails” for two communicating gates may not match Penn ESE370 Fall2014 -- DeHon 11 R rest_of_chip

12. Two Problems 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage Penn ESE370 Fall2014 -- DeHon 12

13. Noise Sources? What did we see in lab when zoomed in on signal transition? Signal coupling –Crosstalk Leakage Ionizing particles Penn ESE370 Fall2014 -- DeHon 13

14. Signals will be degraded 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Penn ESE370 Fall2014 -- DeHon 14

15. Preclass All 1’s  logical output? Penn ESE370 Fall2014 -- DeHon 15

16. Preclass 1.0 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2014 -- DeHon 16

17. Preclass 0.95 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2014 -- DeHon 17

18. Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Penn ESE370 Fall2014 -- DeHon 18

19. Gate Creed Gates should leave the signal “better” than they found it –“better”  closer to the rails Penn ESE370 Fall2014 -- DeHon 19

20. Restoration Discipline Define legal inputs –Gate works if Vin “close enough” to the rail Restoration –Gate produces Vout “closer to rail” This tolerates some drop between one gate and next (between out and in) Call this our “Noise Margin” Penn ESE370 Fall2014 -- DeHon 20

21. Noise Margin V oh – output high V ol – output low V ih – input high V il – input low NM h = V oh -V ih NM l = V il -V ol Penn ESE370 Fall2014 -- DeHon 21 One mechanism, addresses numerous noise sources.

22. Restoration Discipline (getting precise) Define legal inputs –Gate works if Vin “close enough” to the rail –Vin > V ih or Vin < V il Restoration –Gate produces Vout “closer to rail” Vout V oh Penn ESE370 Fall2014 -- DeHon 22 Note: don’t just say V in >V ih  V out >V oh

23. Transfer Function Penn ESE370 Fall2014 -- DeHon 23 What gate is this?

24. Restoring Transfer Function Penn ESE370 Fall2014 -- DeHon 24

25. Decomposing What is gain?  Vout/  Vin| > 1 Where is there gain? Where is there not gain? Dividing point? Penn ESE370 Fall2014 -- DeHon 25

26. Restoring Transfer Function Penn ESE370 Fall2014 -- DeHon 26 V il, V ih = slope -1 points V oh =f(V il ) V ol =f(V ih )

27. Restoring Transfer Function Penn ESE370 Fall2014 -- DeHon 27 V il, V ih = slope -1 points V oh =f(V il ) V ol =f(V ih ) Closer to rail than Vil, Vih Not make much difference on Vout Making Vil lower would reduce NM = Vil-Vol

28. Controlling Value Consider a nor2 gate –If want one input to control the output –What value should the other input be? We call this input the non-controlling input since it does not determine the output What should the non-controlling input value be for a nand2 gate? Penn ESE370 Fall2014 -- DeHon 28

29. Restoring Transfer Function Penn ESE370 Fall2014 -- DeHon 29 For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise)

30. Ideal Transfer Function Penn ESE370 Fall2014 -- DeHon 30

31. Linear Transfer Function? O=Vdd-A Penn ESE370 Fall2014 -- DeHon 31 Noise Margin?

32. Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A Penn ESE370 Fall2014 -- DeHon 32

33. Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? A i+1 = A i -Δ Penn ESE370 Fall2014 -- DeHon 33 Conclude: Linear transfer functions do not provide restoration.

34. Non-linearity Need non-linearity in transfer function Could not have built restoring gates with –R, L, C circuit –Linear elements Penn ESE370 Fall2014 -- DeHon 34

35. Transistor Non-Linearity Penn ESE370 Fall2014 -- DeHon 35

36. All Gates If we hope to assemble design from collection of gates, –Voltage levels must be consistent and supported across all gates –Must adhere to a V il, V ih, V ol, V oh that is valid across entire gate set Penn ESE370 Fall2014 -- DeHon 36

37. Big Idea Need robust logic –Can assemble into any (feed forward) graph –Can tolerate loss and noise –….while maintaining digital abstraction Restoration and noise margins –Every gate makes signal “better” –Design level of noise tolerance Penn ESE370 Fall2014 -- DeHon 37

38. Admin HW2 due Thursday (tomorrow) –Noise margin problem Friday in Ketterer (note combo) –Read through HW3 –Transfer library/schematics to eniac –Be ready to run electric and spice on linux CETS machines own laptop that you bring with you Monday back here Penn ESE370 Fall2014 -- DeHon 38