1. Penn ESE370 Fall2012 -- DeHon 1 ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 6: September 17, 2012 Restoration

2. Today How do we make sure logic is robust –Can assemble into any (feed forward) graph –Can tolerate voltage drops and noise –….while maintaining digital abstraction Penn ESE370 Fall2012 -- DeHon 2

3. Outline Two problems Cascade failure Restoration Transfer Curves Noise Margins Non-linear Penn ESE370 Fall2012 -- DeHon 3

4. Two Problems 1.Output not go to rail –Stops short of Vdd or Gnd 2.Signals may be perturbed by noise V x = V ideal ± V noise Penn ESE370 Fall2012 -- DeHon 4

5. Output not go to Rail CMOS, capacitive load –Mostly doesn’t have problem CMOS, resistive load? Penn ESE370 Fall2012 -- DeHon 5

6. Output not go to Rail Consider: –Vdd=1V –Vin=Gnd (both inputs) –R on (PMOS) = 500Ω –R load = 10KΩ What is Vout? –How close to rail do I need to get? Penn ESE370 Fall2012 -- DeHon 6 R on =500 Ω R load =10K Ω R on =500 Ω

7. Wire Resistance Penn ESE370 Fall2012 -- DeHon 7 Last Wednesday: R wire =10Ω

8. Wire Resistance 1000  m long wire? 1 cm long wire? Length of die side? Penn ESE370 Fall2012 -- DeHon 8

9. Die Sizes Penn ESE370 Fall2012 -- DeHon 9 ProcessorDie SizeTransistor CountProcess Core 2 Extreme X6800143 mm²291 Mio.65 nm Core 2 Duo E6700143 mm²291 Mio.65 nm Core 2 Duo E6600143 mm²291 Mio.65 nm Core 2 Duo E6400111 mm²167 Mio.65 nm Core 2 Duo E6300111 mm²167 Mio.65 nm Pentium D 900280 mm²376 Mio.65 nm Athlon 64 FX-62230 mm²227 Mio.90 nm Athlon 64 5000+183 mm²154 Mio.90 nm http://www.tomshardware.com/reviews/core2-duo-knocks-athlon-64,1282-4.html

10. Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2012 -- DeHon 10

11. Implications What does the circuit really look like for an inverter in the middle of the chip? Penn ESE370 Fall2012 -- DeHon 11 Rwire Rrest_of_chip

12. IR-Drop Since interconnect is resistive and gates pull current off the supply interconnect –The Vdd seen by a gate is lower than the supply Voltage by V drop =I supply x R distribute –Two gates in different locations See different R distribute Therefore, see different V drop Penn ESE370 Fall2012 -- DeHon 12 R rest_of_chip

13. Output not go to Rail CMOS, capacitive load  no problem CMOS, resistive load  voltage divider Due to IR drop, “rails” for two communicating gates may not match Penn ESE370 Fall2012 -- DeHon 13

14. Two Problems 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage Penn ESE370 Fall2012 -- DeHon 14

15. Noise Sources? What did we see in lab when zoomed in on signal transition? Signal coupling –Crosstalk Leakage Ionizing particles IR-drop in signal wiring Penn ESE370 Fall2012 -- DeHon 15

16. Signals will be degraded 1.Output not go to rail –Is this tolerable? 2.Signals may be perturbed by noise –Voltage seen at input to a gate may not lower/higher than input voltage What happens to degraded signals? Penn ESE370 Fall2012 -- DeHon 16

17. Preclass All 1’s  logical output? Penn ESE370 Fall2012 -- DeHon 17

18. Preclass 1.0 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2012 -- DeHon 18

19. Preclass 0.95 inputs, gate: o=1-AB  output voltage? Penn ESE370 Fall2012 -- DeHon 19

20. Degradation Cannot have signal degrade across gates Want to be able to cascade arbitrary set of gates Penn ESE370 Fall2012 -- DeHon 20

21. Gate Creed Gates should leave the signal “better” than they found it –“better”  closer to the rails Penn ESE370 Fall2012 -- DeHon 21

22. Restoration Discipline Define legal inputs –Gate works if Vin “close enough” to the rail Restoration –Gate produces Vout “closer to rail” This tolerates some drop between one gate and text (between out and in) Call this our “Noise Margin” Penn ESE370 Fall2012 -- DeHon 22

23. Noise Margin V oh – output high V ol – output low V ih – input high V il – input low NM h = V oh -V ih NM l = V il -V ol Penn ESE370 Fall2012 -- DeHon 23 One mechanism, addresses numerous noise sources.

24. Restoration Discipline (getting precise) Define legal inputs –Gate works if Vin “close enough” to the rail –Vin > V ih or Vin < V il Restoration –Gate produces Vout “closer to rail” Vout V oh Penn ESE370 Fall2012 -- DeHon 24 Note: don’t just say V in >V ih  V out >V oh

25. Transfer Function Penn ESE370 Fall2012 -- DeHon 25 What gate is this?

26. Restoring Transfer Function Penn ESE370 Fall2012 -- DeHon 26

27. Decomposing Where is there gain? What is gain?  Vout/  vin| > 1 Where is there not gain? Dividing point? Penn ESE370 Fall2012 -- DeHon 27

28. Restoring Transfer Function Penn ESE370 Fall2012 -- DeHon 28 V il, V ih = slope -1 points V oh =f(V il ) V ol =f(V ih )

29. Restoring Transfer Function Penn ESE370 Fall2012 -- DeHon 29 V il, V ih = slope -1 points V oh =f(V il ) V ol =f(V ih ) Closer to rail than Vil, Vih Not make much difference on Vout Making Vil lower would reduce NM = Vil-Vol

30. Restoring Transfer Function Penn ESE370 Fall2012 -- DeHon 30 For multi-input functions, should be worst case. i.e. hold non-controlling inputs at Vil, Vih respectively. (relate preclass exercise)

31. Ideal Transfer Function Penn ESE370 Fall2012 -- DeHon 31

32. Class Ended Here Penn ESE370 Fall2012 -- DeHon 32

33. Linear Transfer Function? O=Vdd-A Penn ESE370 Fall2012 -- DeHon 33 Noise Margin?

34. Linear Transfer Function? Consider two in a row (buffer) O1=Vdd-A What is transfer function to buffer output O2? O2=(Vdd-O1) = Vdd-(Vdd-A)=A Penn ESE370 Fall2012 -- DeHon 34

35. Linear Transfer Function? For buffer: O2=A Consider chain of buffers What happens if A drops a bit between each buffer? A i+1 = A i -Δ Penn ESE370 Fall2012 -- DeHon 35 Conclude: Linear transfer functions do not provide restoration.

36. Non-linearity Need non-linearity in transfer function Could not have built restoring gates with –R, L, C circuit –Linear elements Penn ESE370 Fall2012 -- DeHon 36

37. Transistor Non-Linearity Penn ESE370 Fall2012 -- DeHon 37

38. All Gates If we hope to assemble design from collection of gates, –Voltage levels must be consistent and supported across all gates –Must adhere to a V il, V ih, V ol, V oh that is valid across entire gate set Penn ESE370 Fall2012 -- DeHon 38

39. Admin Wednesday in Ketterer –Lab combo –Read through HW2 –Transfer library/schematics to eniac –Be ready to run electric and spice on linux CETS machines own laptop that you bring with you Friday back here Penn ESE370 Fall2012 -- DeHon 39

40. Big Idea Need robust logic –Can assemble into any (feed forward) graph –Can tolerate loss and noise –….while maintaining digital abstraction Restoration and noise margins –Every gate makes signal “better” –Design level of noise tolerance Penn ESE370 Fall2012 -- DeHon 40