1. Day 3: September 4, 2013 Gates from Transistors
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 3: September 4, 2013
Gates from Transistors
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2. Previously Simplified models for reasoning about transistor circuits
Zeroth-order
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3. Today
How to construct static CMOS gates
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4. Outline Circuit understanding (preclass) Static CMOS
Gate function identification
Static CMOS
Structure
Inverter
Construct gate
Inverting
Cascading
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5. What function? Buffer Vin=Vdd  Vout=Vdd Vin=0  Vout=0
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6. Why Zeroth Order Useful?
Allows us to reason (mostly) at logic level about steady-state functionality of typical gate circuits
Make sure understand logical function (achieve logical function) before worrying about performance details
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7. What gate?
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8. What function?
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9. DeMorgan’s Law
/f = a + b
What is f?
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10. What function?
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11. Static CMOS Gate
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12. Static CMOS Gate Structure
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13. Static CMOS Gate Structure
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14. Static CMOS Gate Structure
Drives rail-to-rail (output is Vdd or Gnd)
Inputs connects to gates  load is capacitive
Once charge capacitive output, doesn’t use energy
(first order)
Output actively driven
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15. Inverter
Out = /in
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16. Inverter
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17. Why zeroth-order adequate?
Static analysis – can ignore capacitors
Capacitive loads – resistances don’t matter
Feed forward for gates –
don’t generally have loops
can work forward from known values
Logic drive rail-to-rail
Don’t have to reason about intermediate voltage levels
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18. What zeroth-order not tell us?
Delay
Dynamics
Behavior if not
Capacitively loaded
Acyclic (if there are Loops)
Rail-to-rail drive
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19. Gate Design Example
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20. Gate Design Design gate to perform: f=(/a+/b)*/c
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21. f=(/a+/b)*/c Strategy: Use static CMOS structure
Design PMOS pullup for f
Use DeMorgan’s Law to determine /f
Design NMOS pulldown for /f
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22. f=(/a+/b)*/c
PMOS Pullup for f?
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23. f=(/a+/b)*/c Use DeMorgan’s Law to determine /f. What is /f ?
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24. f=(/a+/b)*/c
NMOS Pulldown for /f?
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25. f=(/a+/b)*/c a c b
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26. Static CMOS Source/Drains
With PMOS on top, NMOS on bottom
PMOS source always at top (near Vdd)
NMOS source always at bottom (near Gnd)
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27. Inverting Gate
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28. Inverting Stage Each stage of Static CMOS gate is inverting
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29. How do we buffer?
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30. How implement OR?
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31. Cascading Stages
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32. Stages Can always cascade “stages” to build more complex gates
Could simply build nor2 at circuit level and assemble arbitrary logic by combining – universality
but may not be smallest/fastest/least power
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33. Implement: f=a*/b
Pullup?
Pulldown?
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34. f=a*/b
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35. Big Idea Systematic construction of any gate from transistors
Use static CMOS structure
Design PMOS pullup for f
Use DeMorgan’s Law to determine /f
Design NMOS pulldown for /f
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36. Admin Office hours Thursday: HW1 due Friday in Detkin (RCA) Lab
Today only: Spencer 7:30—8:30pm Ketterer
Monday: Spencer 5-6pm Ketterer
Tuesday: Andre 4:15-5:30pm Levine 270
Thursday: HW1 due
identify gates; use electric
Friday in Detkin (RCA) Lab
Please read through HW2, Lab1 details
Bring USB drive with you to lab on Friday to store waveforms
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